• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.57-67
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• 2002

Increased signal speed can be obtained in three ways: changing the layout and/or the ratio of the width to thickness of the metal lines, decreasing the specific resistance of the interconnect metal, and decreasing the dielectric constant of the insulating material (intermetal dielectric). Further advancement cannot be expected from changing layout or decreasing specific resistance. The only alternative is to use an insulating material with a lower dielectric constant than other ones used presently. A large variety of polymers has been proposed for use as materials with low dielectric constants for applications in microelectronics. In this review, the properties of selected polymers as well as various fabrication methods for polymer thin films are discussed. Based on the properties described so far, and the requirements for applications as intermetal dielectric material, the possibilities for further developments also are discussed.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.11a
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• pp.159-159
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• 2007

In order to reduce a signal delay in ULSI, low resistive metal and intermetal dielectric material of low dielectric constant are required. Ordered mesoporous silica film is proper to intermetal dielectric due to its low dielectric constant and superior mechanical properties. In this study, ordered mesoporous silica films was synthesized using TEOS (tetraethoxysilane) / MTES (methyltriethoxysilane) mixed silica precursor and Brij-$76^{(R)}$ surfactant. These films had the porosity of 40% and dielectric constant of 2.5. To lower dielectric constant, the ordered mesoporous silica films were surface-modified by HMDS (hexamethyldisilazane) treatment. HMDS substituted -OH groups on the surface of silica wall for -Si$(CH_3)_3$ groups. After the HMDS treatment, ordered mesoporous silica films were calcined at various calcination temperatures. Through the investigation, it was concluded that the proper calcination temperature is necessary as aspects of structural, electrical, and mechanical properties.

• Proceedings of the Materials Research Society of Korea Conference
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• 1996.11a
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• pp.45-45
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• 1996

• Journal of the Korean Ceramic Society
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• v.45 no.1
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• pp.48-53
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• 2008

In order to reduce signal delay in ULSI, an intermetal material of low dielectric constant is required. Ordered mesoporous silica film is proper to intermetal dielectric due to its low dielectric constant and superior mechanical properties. The ordered mesoporous silica film prepared by TEOS (tetraethoxysilane) / MTES (methyltriethoxysilane) mixed silica precursor and Brij-76 surfactant was surface-modified by HMDS (hexamethyldisilazane) treatment to reduce its dielectric constant. HMDS can substitute $-Si(CH_3)_3$ groups for -OH groups on the surface of silica wall. In order to modify interior silica wall, HMDS was treated by two different processes except the conventional spin coating. One process is that film is dipped and stirred in HMDS/n-hexane solution, and the other process is that film is exposed to evaporated HMDS. Through the investigation with different HMDS treatment, it was concluded that surface modification in evaporated HMDS was more effective to modify interior silica wall of nano-sized pores.

• Journal of the Korean Vacuum Society
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• v.4 no.S1
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• pp.130-137
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• 1995

Deopsition of thermal quality SiO2 using a high density plasma ECR CVD process has been demonstrated to give void and seam free gap fill of high aspect ratio metallization structures with a simple oxygen-silane chemistry. This is achieved by continuous sputter etching of the film during the deposition process. A two-step process is utilized to deposit a composite layer for higher manufacturing efficiency. The first step, which has a deposition rate of approximately 0.5 $\mu$m/min., is used to provide complete gap fill between the metal lines. The second step, which has a deposition rate of up to 1.5 $\mu$m/min., is used to deposit a total thickness of 2.0$\mu$m for the intermetal dielectric film. The topography of this composite film is very compatible with subsequent chemicl mechanical polishing(CMP) planarization processing.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• Journal of Korean Vacuum Science & Technology
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• v.2 no.1
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• pp.25-31
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• 1998

The reliability of fluorine doped silicon oxide (SiOF) films for intermetal dielectrics in multilevel interconnections of ultra-large scale integrated circuits (ULSIs) is investigated. SiOF films were deposited by electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECRPECVD) using H-free source gases, i.e., SiF4 and O2. The effect of post plasma treatment on the moisture absorption and dielectric properties of SiOF films was carried out I terms of air exposure time, The reliability test of Cu/TiN/SiOF/Fi specimen was carried out in terms of temperature by rapid thermal annealing (RTA) in N2 ambient. After O2 plasma treatment,, no appreciable peak directly related to moisture absorption was detected. The capacitance-voltage (C-V) characteristics of the O2 plasma treated SiOF film showed that the film remained to hold the sound dielectric properties even after boiling treatment. The Cu/TiN/SiOF/Si system was found to be reliable up to $600^{\circ}C$.

• Electrical & Electronic Materials
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• v.8 no.2
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• pp.171-175
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• 1995

Optimum condition of remote plasma enhanced chemical vapor deposition using orthogonal array method was chosen. Characteristics of oxide films deposited by RPECVD with SiH$_{4}$ and N$_{2}$O gases were investigated. Etching rate of the optimized SiO$_{2}$ films in P-etchant was about 6[A/s] that was almost the same as that the high temperature thermal oxide. The films showed high dielectric breakdown field of more than 7[MV/cm] and a resistivity of 8*10$^{13}$ [.ohmcm] around at 7[MV/cm]. The interface trap density of SiO$_{2}$/Si interface around the midgap derived from the high frequency C-V curve was about 5*10$^{10}$ [/cm$^{2}$eV]. It was observed that the dielectric constant of the optimized SiO$_{2}$ film was 4.29.

• Journal of the Korean Vacuum Society
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• v.7 no.3
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• pp.167-272
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• 1998

The fluorine doped silicon oxide (SiOF) intermetal dielectric (IMD) films havc been of interest due to their lower dielectric constant and compatibility with existing process tools. However, instability issues related to hond and increasing dielectric constant due to water absorption when the SiOF film was exposured to atmospheric ambient. Therefore, the purpose nf this research is to study the effect of post oxygen plasma treatment on the resistance of nioisture absorption and reliability of SiOF film. Improvement of moisture ahsorption resistance of SiOF film is due to the forming of thin $SiO_2$ layer at the SiOF film surface. It is thought that the main effect of the improvement of moisture absorption resistance was densification of the top layer and reduction in the numher of Si-F honds that tend to associate with OH honds. However, the dielectric constant was inucased when plasma treatment time is above 5 min. In this study, therefore, it is thought that the proper plasma treatment time is 3 min when plasma treatment condition is 700 W of microwave power, 3 mTorr of process pressure and $300^{\circ}C$ of substrate temperature.

• Proceedings of the KIEE Conference
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• 1987.07a
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• pp.424-428
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• 1987

A $2{\mu}m$ CMOS P-well double metal technology has been developed. Phosphorus deep implantation and drive-in diffusion steps were utilized to prevent the low voltage bulk punch through in the short channel, 1.6[${\mu}m$] Leff, PMOS device. Double metal process with the rules of 5[${\mu}m$] 1st metal pitch and 7[${\mu}m$] 2nd metal pitch was successfully implemented by using VLTO, low temperature oxide, as on intermetal dielectric.