• 마이크로전자및패키징학회지
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• 제9권3호
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• pp.57-67
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• 2002

반도체 칩의 신호처리속도를 향상시키기 위한 방법에는 세 가지가 있다. 첫 번째 방법은 금속배선의 배치(layout)를 바꾸는 것이고, 두 번째 방법은 배선으로 사용되는 금속의 비저항을 감소시키는 것이며, 세 번째 방법은 절연재료(insulating material)의 유전상수(dielectric constant)를 감소시키는 것이다. 첫 번째나 두 번째의 방법에 대해서는 많은 연구가 이루어졌고, 지금도 연구가 이루어지고 있다. 그러나 첫 번째나 두 번째의 방법을 통하여 얻을 수 있는 신호처리속도의 향상보다는 세 번째 방법을 통하여 얻을 수 있는 신호처리속도의 향상이 더 크다. 본 논문에서는 먼저 마이크로전자에 응용되기 위한 절연재료의 요구조건을 살펴보고, 지금까지 개발된 저유전율 고분자재료들을 간략하게 소개할 예정이다. 아울러 유전상수를 낮추기 위하여 최근 개발된 기공을 갖는 고분자재료들과 이들을 제조하기 위한 공정에 대해서도 간략하게 소개할 예정이다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 추계학술대회 논문집
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• pp.159-159
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• 2007

In order to reduce a signal delay in ULSI, low resistive metal and intermetal dielectric material of low dielectric constant are required. Ordered mesoporous silica film is proper to intermetal dielectric due to its low dielectric constant and superior mechanical properties. In this study, ordered mesoporous silica films was synthesized using TEOS (tetraethoxysilane) / MTES (methyltriethoxysilane) mixed silica precursor and Brij-$76^{(R)}$ surfactant. These films had the porosity of 40% and dielectric constant of 2.5. To lower dielectric constant, the ordered mesoporous silica films were surface-modified by HMDS (hexamethyldisilazane) treatment. HMDS substituted -OH groups on the surface of silica wall for -Si$(CH_3)_3$ groups. After the HMDS treatment, ordered mesoporous silica films were calcined at various calcination temperatures. Through the investigation, it was concluded that the proper calcination temperature is necessary as aspects of structural, electrical, and mechanical properties.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1996년도 재료학회 추계학술발표회
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• pp.45-45
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• 1996

• 한국세라믹학회지
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• 제45권1호
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• pp.48-53
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• 2008

In order to reduce signal delay in ULSI, an intermetal material of low dielectric constant is required. Ordered mesoporous silica film is proper to intermetal dielectric due to its low dielectric constant and superior mechanical properties. The ordered mesoporous silica film prepared by TEOS (tetraethoxysilane) / MTES (methyltriethoxysilane) mixed silica precursor and Brij-76 surfactant was surface-modified by HMDS (hexamethyldisilazane) treatment to reduce its dielectric constant. HMDS can substitute $-Si(CH_3)_3$ groups for -OH groups on the surface of silica wall. In order to modify interior silica wall, HMDS was treated by two different processes except the conventional spin coating. One process is that film is dipped and stirred in HMDS/n-hexane solution, and the other process is that film is exposed to evaporated HMDS. Through the investigation with different HMDS treatment, it was concluded that surface modification in evaporated HMDS was more effective to modify interior silica wall of nano-sized pores.

• 한국진공학회지
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• 제4권S1호
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• pp.130-137
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• 1995

Deopsition of thermal quality SiO2 using a high density plasma ECR CVD process has been demonstrated to give void and seam free gap fill of high aspect ratio metallization structures with a simple oxygen-silane chemistry. This is achieved by continuous sputter etching of the film during the deposition process. A two-step process is utilized to deposit a composite layer for higher manufacturing efficiency. The first step, which has a deposition rate of approximately 0.5 $\mu$m/min., is used to provide complete gap fill between the metal lines. The second step, which has a deposition rate of up to 1.5 $\mu$m/min., is used to deposit a total thickness of 2.0$\mu$m for the intermetal dielectric film. The topography of this composite film is very compatible with subsequent chemicl mechanical polishing(CMP) planarization processing.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1994년도 추계학술대회 논문집
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• pp.171-174
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• 1994

The drive towards ultra-large-scale integrated circuits a continuous intermetal dielectric films for multi layer interconection. Optimum condition of remote plasma enhanced chemical vapour deposition(RPECVD) was achieved by orthogonal array method. Chracteristics of SiO$_2$ films deposited by using remote PECVD with N$_2$O gas were investigated. Etching rate of SiO$_2$ films in P-echant was about 6[A/s] that was the same as the thermal oxide. The films a showed high breakdown voltage of 7(MV/cm) and a resistivity of Bx10$\^$13/[$\Omega$cm] at 7(MV/cm). The interface Trap density of SiO$_2$ has been shown excel lent properties of 5x10$\^$10/[/$\textrm{cm}^2$eV]. It was observed that the dielectric constant dropped to a value of 4. 29 for 150 [W] RF power.

• Journal of Korean Vacuum Science & Technology
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• 제2권1호
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• pp.25-31
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• 1998

The reliability of fluorine doped silicon oxide (SiOF) films for intermetal dielectrics in multilevel interconnections of ultra-large scale integrated circuits (ULSIs) is investigated. SiOF films were deposited by electron cyclotron resonance plasma-enhanced chemical vapor deposition (ECRPECVD) using H-free source gases, i.e., SiF4 and O2. The effect of post plasma treatment on the moisture absorption and dielectric properties of SiOF films was carried out I terms of air exposure time, The reliability test of Cu/TiN/SiOF/Fi specimen was carried out in terms of temperature by rapid thermal annealing (RTA) in N2 ambient. After O2 plasma treatment,, no appreciable peak directly related to moisture absorption was detected. The capacitance-voltage (C-V) characteristics of the O2 plasma treated SiOF film showed that the film remained to hold the sound dielectric properties even after boiling treatment. The Cu/TiN/SiOF/Si system was found to be reliable up to $600^{\circ}C$.

• E2M - 전기 전자와 첨단 소재
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• 제8권2호
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• pp.171-175
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• 1995

Optimum condition of remote plasma enhanced chemical vapor deposition using orthogonal array method was chosen. Characteristics of oxide films deposited by RPECVD with SiH$_{4}$ and N$_{2}$O gases were investigated. Etching rate of the optimized SiO$_{2}$ films in P-etchant was about 6[A/s] that was almost the same as that the high temperature thermal oxide. The films showed high dielectric breakdown field of more than 7[MV/cm] and a resistivity of 8*10$^{13}$ [.ohmcm] around at 7[MV/cm]. The interface trap density of SiO$_{2}$/Si interface around the midgap derived from the high frequency C-V curve was about 5*10$^{10}$ [/cm$^{2}$eV]. It was observed that the dielectric constant of the optimized SiO$_{2}$ film was 4.29.

• 한국진공학회지
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• 제7권3호
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• pp.167-272
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• 1998

ECR plasma CVD를 이용한 SiOF박막은 낮은 유전상수를 가지고 있으며, 기존의 공정과의 정합성이 우수해 다층배선 공정에 채용이 유망한 재료이지만 수분의 흡수로 인한 유전율의 상승과 후속공정의 안정성이 문제점으로 부각되고 있다. 따라서 본 연구에서는 SiOF박막의 내흡습성과 후속공정에서의 안정성을 향상시키기 위하여 SiOF박막을 증착한 후 후속 산소 플라즈마 처리를 행하였다. SiOF박막은 산소 플라즈마 처리를 수행함으로써 SiOF박막의 밀도가 증가하고, 수분과의 친화력이 강한 Si-F 결합이 감소하는 것이 주요한 원인으로 사료된다. 하지만 플라즈마 처리 시간이 5분 이상으로 증가하면 유전율의 증가가 일어난다. 따라서 본 실험에서는 산소 플라즈마 처리조건이 마이크로파 전력이 700W, 공정 압력이 3mTorr, 기판온도가 $300^{\circ}C$일 경우 플라즈마 처리시간은 3분이 적당한 것으로 생각 된다.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1987년도 전기.전자공학 학술대회 논문집(I)
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• pp.424-428
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• 1987

A $2{\mu}m$ CMOS P-well double metal technology has been developed. Phosphorus deep implantation and drive-in diffusion steps were utilized to prevent the low voltage bulk punch through in the short channel, 1.6[${\mu}m$] Leff, PMOS device. Double metal process with the rules of 5[${\mu}m$] 1st metal pitch and 7[${\mu}m$] 2nd metal pitch was successfully implemented by using VLTO, low temperature oxide, as on intermetal dielectric.