• Journal of the Microelectronics and Packaging Society
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• v.23 no.4
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• pp.19-24
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• 2016

Along the few nano sizing dimensions of integrated circuit (IC) devices, acceptable interlayer material for design is inevitable. The interlayer which include dielectric, interconnect, barrier etc. needs to achieve not only electrical properties, but also mechanical properties for endure post manufacture process and prolonging life time. For developing intermetallic dielectric (IMD) the mechanical issues with post manufacturing processes were need to be solved. For analyzing specific structural problem and material properties Raman spectroscopy was performed for various researches in Si semiconductor based materials. As improve of the laser and charge-coupled device (CCD) technology the total effectiveness and reliability was enhanced. For thin film as IMD developed material could be analyzed by Raman spectroscopy, and diverse researches of developing method to analyze thin layer were comprehended. Also In-situ analysis of Raman spectroscopy is introduced for material forming research.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.3
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• pp.13-17
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• 2000

The electrical properties of polyimide for interlayer dielectric applications are investigated with ECR (Electron Cyclotron Resonance) etching process. ECR etching with $Cl_2$-based plasma, generally used for aluminum etching, results in an increase in the dielectric constant of polyimide, while $SF_{6}$ plasma exhibits a high polyimide etch rate and a reducing effect of the dielectric constant. The leakage current of the polyimide is significantly suppressed after plasma exposure. Combination of Al etching with $Cl_2$plasma and polyimide etching with $SF_{6}$ plasma is expected as a good tool for realizing the multilevel metallization structures.

• Journal of the Semiconductor & Display Technology
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• v.8 no.3
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• pp.19-23
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• 2009

We have studied dielectric characteristics of low-k interlayer dielectric materials was fabricated by plasma enhanced chemical vapor deposition (PECVD). BTMSM precursor was introduced with the flow rates from 24 sccm to 32 sccm by 2 sccm step in the constant flow rate of 60 sccm $O_2$. Then, SiOCH thin film deposited at room temperature was annealed at temperature of $400^{\circ}C$ and $500^{\circ}C$ for 30 minutes in vacuum. The vibrational groups of SiOCH thin films were analyzed by FT/IR absorption lines, and the dielectric constant of the low-k SiOCH thin films were obtained by measuring C-V characteristic curves. With the result that FTIR analysis, as BTMSM flow rate increase, relative carbon content of SiOCH thin film increased from 29.5% to 32.2%, and increased by 32.8% in 26 sccm specimen after $500^{\circ}C$ annealing. Dielectric constant was lowest by 2.32 in 26 sccm specimen, and decreased more by 2.05 after $500^{\circ}C$ annealing. Also, leakage current is lowest by $8.7{\times}10^{-9}A/cm^2$ in this specimen. In the result, shift phenomenon of chemical bond appeared in SiOCH thin film that BTMSM flow rate is deposited by 26 sccms, and relative carbon content was highest in this specimen and dielectric constant also was lowest value

• Proceedings of the Korean Society of Precision Engineering Conference
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• 1997.10a
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• pp.935-938
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• 1997

Recently, the minimum line width shows a tendency to decrease and the multi-level increase in semiconductor. Therefore, a planarization technique is needed and chemical mechanical polishing(CMP) is considered as one of the most suitable process. CMP accomplishes a high polishing performance and a global planarization of high quality. But there are several defects in CMP such as micro-scratches, abrasive contaminations, and non-uniformity of polished wafer edges. Wet etching include of Spin-etching can improve he defects of CMP. It uses abrasive-free chemical solution instead of slurry. On this study, ILD(INterlayer-Dielectric) was removed by CMP and wet-etching methods in order to investigate the superiority of wet etching mechanism. In the thin film wafer, the results were evaluated at a viewpoint of material removal rate(MRR) and within wafer non-uniformity(WIWNU). And pattern step height was also compared for planarization characteristics of the patterned wafer.

• Journal of the Korean Chemical Society
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• v.53 no.1
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• pp.42-50
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• 2009

The dielectric-spectroscopic and ac conductivity studies firstly carried out on layered manganese doped Sodium Lithium Trititanates ($Na_{1.9}Li_{0.1}Ti_3O_7$). The dependence of loss tangent (Tan$\delta$), relative permittivity ($\varepsilon_r$) and ac conductivity ($\sigma_{ac}$) in temperature range 373-723K and frequency range 100Hz-1MHz studied on doped derivatives. Various conduction mechanisms are involved during temperature range of study like electronic hopping conduction in lowest temperature region, for MSLT-1 and MSLT-2. The hindered interlayer ionic conduction exists with electronic hopping conduction for MSLT-3. The associated interlayer ionic conduction exists in mid temperature region for all doped derivatives. In highest temperature region modified interlayer ionic conduction along with the polaronic conduction, exist for MSLT-1, MSLT-2, and only modified interlayer ionic conduction for MSLT-3. The loss tangent (Tan$\delta$) in manganese-doped derivatives of layered $Na_{1.9}Li_{0.1}Ti_3O_7$ ceramic may be due to contribution of electric conduction, dipole orientation, and space charge polarization. The corresponding increase in the values of relative permittivity may be due to increase in number of dipoles in the interlayer space while the corresponding decrease in the values of relative permittivity may be due to the increase in the leakage current due to the higher doping.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.21 no.4
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• pp.362-367
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• 2008

We have Manufactured the low-k dielectric interlayer fabricated by plasma enhanced chemical vapor deposition (PECVD), The thin film of SiOCH is studied correlation between components and Dielectric constant. The precursor was evaporated and introduced with the flow rates from 16 sccm to 25 sccm by 1sccm step in the constant flow rate of 60 sccm $O_2$ in process chamber. The chemical characteristics of SiOCH were analyzed by measuring FT/IR absorption lines and obtained each dielectric constant measuring C-V. Then compare respectively. ILD of BTMSM/$O_2$ could have low dielectric constant about $k\sim2$, and react sensitively. Also dielectric constant could be decreased by the effects of decreasing $CH_3$ and growing Si-O-Si(C) after annealing process.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.57-67
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• 2002

Increased signal speed can be obtained in three ways: changing the layout and/or the ratio of the width to thickness of the metal lines, decreasing the specific resistance of the interconnect metal, and decreasing the dielectric constant of the insulating material (intermetal dielectric). Further advancement cannot be expected from changing layout or decreasing specific resistance. The only alternative is to use an insulating material with a lower dielectric constant than other ones used presently. A large variety of polymers has been proposed for use as materials with low dielectric constants for applications in microelectronics. In this review, the properties of selected polymers as well as various fabrication methods for polymer thin films are discussed. Based on the properties described so far, and the requirements for applications as intermetal dielectric material, the possibilities for further developments also are discussed.

• Journal of Adhesion and Interface
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• v.22 no.3
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• pp.91-97
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• 2021

By introducing an organic interlayer on the Parylene C dielectric surface, the electrical device performances and the operating stabilities of organic field-effect transistors (OFETs) were improved. To achieve this goal, hexamethyldisilazane (HMDS) and octadecyltrichlorosilane (ODTS), as the organic interlayer materials, were used to control the surface energy of the Parylene C dielectrics. For the bare case used with the pristine Parylene C dielectrics, the field-effect mobility (μ_FET) and threshold voltage (V_th) of dinaphtho[2,3-b:2',3'-f ]thieno[3,2-b]- thiophene (DNTT) FET devices were measured at 0.12 cm²V^-1s^-1 and - 5.23 V, respectively. On the other hand, the OFET devices with HMDS- and ODTS-modified cases showed the improved μ_FET values of 0.32 and 0.34 cm²V^-1s^-1, respectively. More important point is that the μ_FET and V_th of the DNTT FET device with the ODTS-modified Parylene C dielectric presented the smallest changes during a repeated measurement of 1000 times, implying that it has the most stable operating stability. The results could be meaned that the organic interlayer, especially ODTS, effectively covers the Parylene C dielectric surface with alkyl chains and reduces the charge trapping at the interface region between active layer and dielectric, thereby improving the electrical operating stability.

• Journal of the Korean Vacuum Society
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• v.16 no.6
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• pp.446-452
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• 2007

[ $(Pb_{1.1},La_{0.08})(Zr_{0.65}.Ti_{0.35})O_3$ ] thin films on the $Pt/Ti/SiO_2/Si$, $TiO_2(interlayer)/Pt/Ti/SiO_2/Si$ substrate were fabricated by the R.F. magnetron-sputtering method and considered their characteristics depending on $TiO_2$ interlayer. Changing the deposition conditions of $TiO_2$ interlayer, we obtained $TiO_2$ anatase single phase and rutile single phase. PLZT was deposited on these substrates and analyzed by x-ray diffraction(XRD) for there crystallinity and orientation. To investigate $PLZT-TiO_2$, $TiO_2-Pt$ interface, glow discharge spectrometer(GDS) analysis was carried out and we performed electrical measurements for dielectric properties of PLZT thin films. The PLZT thin film on $TiO_2$ anatase interlayer was found to have (110)-preferred orientation and 12.6 ${\mu}C/cm^2$ remaining polarization value.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.08a
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• pp.214.2-214.2
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• 2013

Device performance for the 45 and 32 nm node CMOS technology requires the integration of ultralow-k materials. To lower the dielectric constant for PECVD and spin-on materials, partial replacement of the solid network with air (k=1.01) appears to be more intuitive and direct option. This can be achieved introducting of second "labile" phase during depositoin that is removed during a subsequent UV curing and annealing step. Besides, with shrinking line dimensions the resistivity of barrier films cannot meet the International Technology Roadmap for Semiconductors (ITRS) requirements. To solve this issue self-forming diffusion barriers have drawn attention for great potential technique in meeting all ITRS requirments. In this present work, we report a Cu-V alloy as a materials for the self-forming barrier process. And we investigated diffusion barrier properties of self-formed layer on low-k dielectrics with or without UV curing treatment. Cu alloy films were directly deposited onto low-k dielectrics by co-sputtering, followed by annealing at various temperatures. X-ray diffraction revealed Cu (111), Cu (200) and Cu (220) peaks for both of Cu alloys. The self-formed layers were investigated by transmission electron microscopy. In order to compare barrier properties between V-based interlayer on low-k dielectric with UV curing and interlayer on low-k dielectric without UV curing, thermal stability was measured with various heat treatment temperature. X-ray photoelectron spectroscopy analysis showed that chemical compositions of self-formed layer. The compositions of the V based self-formed barriers after annealing were strongly dominated by the O concentration in the dielectric layers.