• KIPS Transactions on Computer and Communication Systems
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• v.12 no.5
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• pp.157-164
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• 2023

Specifying the semantic structure for functional interfaces and lambda expressions, which are the latest features of Java, can be referenced when designing similar functions in the future, and is also required in the process of standardizing or implementing an optimized translator. In this study, action equation 3.0 is newly proposed to express the static and dynamic semantic structure of functional interfaces and lambda expressions by modifying and upgrading the existing expressions to express the semantic structures of java functional interfaces and lambda expressions. Measure the execution time of java programs by implementing the semantic structure specified in action equation 3.0 in java, and prove that action equation 3.0 is a real semantic structure that can be implemented through simulation. The superiority of this action equation 3.0 is to be confirmed by comparing the action equation 3.0 specified in the four areas of readability, modularity, extensibility and flexibility with the existing representative semantic expression methods.

• Journal of Internet Computing and Services
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• v.16 no.5
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• pp.29-38
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• 2015

The Energy Storage System stores electricity for later use. This system can store electricity from legacy electric power systems or renewable energy systems into a battery device when demand is low. When there is high electricity demand, it uses the electricity previously stored and enables efficient energy usage and stable operation of the electric power system. It increases the energy usage efficiency, stabilizes the power supply system, and increases the utilization of renewable energy. The recent increase in the global interest for efficient energy consumption has increased the need for an energy storage system that can satisfy both the consumers' demand for stable power supply and the suppliers' demand for power demand normalization. In general, an energy storage system consists of a Power Conditioning System, a Battery Management System, a battery cell and peripheral devices. The specifications of the subsystems that form the energy storage system are manufacturer dependent. Since the core component interfaces are not standardized, there are difficulties in forming and operating the energy storage system. In this paper, the design of the profile structure for energy storage system and realization of private profiling system for energy storage system is presented. The profiling system accommodates diverse component settings that are manufacturer dependent and information needed for effective operation. The settings and operation information of various PCSs, BMSs, battery cells, and other peripheral device are analyzed to define profile specification and structure. A profile adapter software that can be applied to energy storage system is designed and implemented. The profiles for energy storage system generated by the profile authoring tool consist of a settings profile and operation profile. Setting profile consists of configuration information for energy device what composes energy saving system. To be more specific, setting profile has three parts of category as information for electric control module, sub system, and interface for communication between electric devices. Operation profile includes information in relation to the method in which controls Energy Storage system. The profiles are based on standard XML specification to accommodate future extensions. The profile system has been verified by applying it to an energy storage system and testing charge and discharge operations.

• Journal of KIISE:Information Networking
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• v.35 no.5
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• pp.409-414
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• 2008

In mobile ad hoc networks, most of on demand routing protocols such as DSR and AODV do not deal with traffic load during the route discovery procedure. To solve the congestion and achieve load balancing, many protocols have been proposed. However, the existing load balancing schemes has only considered avoiding the congested route in the route discovery procedure or finding an alternative route path during a communication session. To mitigate this problem, we have proposed a new scheme which considers the packet bursting mechanism in congested nodes. The proposed packet bursting scheme, which is originally introduced in IEEE 802.11e QoS specification, is to transmit multiple packets right after channel acquisition. Thus, congested nodes can forward buffered packets promptly and minimize bottleneck situation. Each node begins to transmit packets in normal mode whenever its congested status is dissolved. We also propose two threshold values to define exact overloaded status adaptively; one is interface queue length and the other is buffer occupancy time. Through an experimental simulation study, we have compared and contrasted our protocol with normal on demand routing protocols and showed that the proposed scheme is more efficient and effective especially when network traffic is heavily loaded.

• 제어로봇시스템학회:학술대회논문집
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• 2004.08a
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• pp.981-985
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• 2004

In this paper we designed the motor control IP Core and evaluate its quality from the viewpoint of IP reuse. The most attractive merit of this methodology, so called IP-based hardware design, is hardware reuse. Although various vendors designed hardware with the same specification and got the same functional results, all that IPs is not the same quality in the reuse aspect. As tremendous calls for SoC have been increased, associated research about IP quality standard, VSIA(Virtual Socket Interface Alliance) and STARC(Semiconductor Technology Academic Research Center), has been doing best to make the IP quality evaluation system. And they made what conforms to objective IP design standard. We suggest the methodology to evaluate our own designed motor control IP quality with this standard. To attain our goal, we designed motor control IP that could control the motor velocity and position with feedback compensation algorithm. This controller has some IP blocks : digital filter, quadrature decoder, position counter, motion compensator, and PWM generator. Each block's functionality was verified by simulator ModelSim and then its quality was evaluated. To evaluate the core, We use Vnavigator for lint test and ModelSim for coverage check. During lint process, We adapted the OpenMORE's rule based on RMM (Reuse Methodology Manual) and it could tell us our IP's quality in a manner of the scored value form. If it is high, its quality is also high, and vice versa. During coverage check ModelSim-SE is used for verifying how our test circuits cover designs. This objective methods using well-defined commercial coverage metrics could perform a quantitative analysis of simulation completeness. In this manner, We evaluated the designed motor control IP's quality from the viewpoint of reuse. This methodology will save the time and cost in designing SoC that should integrate various IPs. In addition to this, It can be the guide for comparing the equally specified IP's quality. After all, we are continuously looking forward to enhancing our motor control IP in the aspect of not only functional perfection but also IP reuse to prepare for the SoC-Compliant motor control IP design.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.7
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• pp.402-413
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• 2004

This paper presents an Implementation of Korean standard 128-bit block cipher SEED for the small (8 or 16-bits) embedded system using a low-cost FPGA(Field Programmable Gate Array) chip. Due to their limited computing and storage capacities most of the 8-bits/16-bits small embedded systems require a separate and dedicated cryptography processor for data encryption and decryption process which require relatively heavy computation job. So, in order to integrate the SEED with other logic circuit block in a single chip we need to invent a design which minimizes the area demand while maintaining the proper performance. But, the straight-forward mapping of the SEED specification into hardware design results in exceedingly large circuit area for a low-cost FPGA capacity. Therefore, in this paper we present a design which maximize the resource sharing and utilizing the modern FPGA features to reduce the area demand resulting in the successful implementation of the SEED plus interface logic with single low-cost FPGA. We achieved 66% area accupation by our SEED design for the XC2S100 (a Spartan-II series FPGA from Xilinx) and data throughput more than 66Mbps. This Performance is sufficient for the small scale embedded system while achieving tight area requirement.

• Journal of Astronomy and Space Sciences
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• v.17 no.1
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• pp.53-66
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• 2000

We developed low light CCD imaging system using thermoelectric cooling method collaboration with a company to design a commercial model. It consists of Kodak KAF-0401E(768$\times$512 pixels) CCD chip, thermoelectric module manufactured by Thermotek. This TEC system can reach an operative temperature of $-25^{\circ}C$. We employed an Uniblitz VS25s shutter and it has capability a minimum exposure time 80ms. The system components are an interface card using a Korea Astronomy Observatory (hereafter KAO) ISA bus controller, image acquisition with AD9816 chip, that is 12bit video processor. The performance test with this imaging system showed good operation within the initial specification of our design. It shows a dark current less than 0.4e-/pixel/sec at a temperature of $-10^{\circ}C$, a linearity 99.9$\pm$0.1%, gain 4.24e-/adu, and system noise is 25.3e-(rms). For low temperature CCD operation, we designed a TEC, which uses a one-stage peltier module and forced air heat exchanger. This TEC imaging system enables accurate photometry($\pm$0.01mag) even though the CCD is not at 'conventional' cryogenic temperatures(140k). The system can be a useful instrument for any other imaging applications. Finally, with this system, we obtained several images of astronomical objects for system performance tests.

• Spatial Information Research
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• v.9 no.1
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• pp.73-89
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• 2001

In the recent rapidly changing technology environment the computerization of administration business using GIS is driven or will be driven to give improved information services for the people by local government or central government with huge budget. Development of GIS for local governments is investigated with huge budge. Development of GIS for local governments is investigated to prevent local government from investing redundant money and to reuse the existing investment at this time. The purpose of this study is finding the development method of Land Management Information System (LMIS) to give service and share data in various computing environment of local governments. To do this, we have to develop LMIS as open system with interoperability and we explain it with a focus to framework of Open LMIS. According to recent trend of technology we developed Open LMIS for convenient maintenance with nationwide LMIS expansion at hand. This system was developed at the $\ulcorner$Land Management Information System Development$\lrcorner$project which was managed by Ministry of Construction and Transportation (MOCT). GIS application was based on OpenGIS CORBA specification for development of standard interface and RUP(Rational Unified Process) for development method and LML(Unified Modeling Language) for system design. Developed systems were land administration system for local government, spatial planning support system for regional government, and land policy support system for MOCT.

• Spatial Information Research
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• v.9 no.1
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• pp.107-124
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• 2001

The purpose of this research is to develop system and to establish methodology for managing spatial Database in Land Management Information System(LMIS). Spatial Database which is used by a various public department such as parcel survey and registry, land use planning and Land value appraisal in local government, is composed of parcel map, topographic map and zoning map. Spatial data has been constructed and managed by various department and then hard to maintain accuracy and coinsistency. So, it is important to establish the basic data management concept that source data(ex : parcel map, topographic map, zoning map, etc.) should be managed by responsible department. at the same time, application data for bussiness (ex : individual parcel price map) must be recomposed from base map by it's own objects. This is, Spatial data management system (SDMS) should be designed, developed according to this concept for managing consistency among data, reducing construction and management cost of database. Our SDMS was developed based on Open LMIS middleware architecture using OpenGIS CORBA specification for standard interface, RUP(Rational Unified Process) for development methodology, UML(Unified Modeling Language) for system design and VisiBroker, C++, CAD system for system implementation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37C no.11
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• pp.1094-1103
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• 2012

Recently, software industry regarding national defense increases system development of distributed simulation system of M&S based to overcome limit of resource and expense. It is one of key technologies for offering of mutual validation among objects and reuse of objects which are discussed for developing these systems. RTI, implementation of HLA interface specification as software providing these technologies uses Federation Object Model for exchanging information with joined federates in the federation and each federate has a characteristic that is supposed to have identical FOM in the federation. This technology is a software which is to provide the core technology which was suggested by the United state's military M&S standard framework. Simulator, virtual simulation, and inter-connection between military weapons system S/W which executes on network which is M&S's core base technology, and it is a technology which also can be used for various inter-connection between S/W such as game and on-line phone. These days although RTI is used in military war game or tactical training unit field, there is none in Korea. Also, it is used in mobile-game, distribution game, net management, robot field, and other civilian field, but the number of examples are so small and informalized. Through this developing project, we developed the core technique and RTI software and provided performance of COTS level to improve communication algorithms.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.39 no.6
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• pp.553-558
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• 2011

This paper describes the development and test result of S-band Transmitter flight model(FM) of STSAT-3 by satellite research center(SaTReC), KAIST. The communication sub-system of STSAT-3 is consist of two different frequency band channels, S-band for Telemetry & Command and X-band for mission data. S-band Transmitter(STX) functionally made of modulator, frequency synthesizer, power amp and DC/DC converter. The transmission data is modulated by FSK(Frequency Shift Keying) and the interface between spacecraft sub-module and STX is RS-422 standard method. The FM STX is based on modular design. The RF output power of STX is 1.5W(31.7dBm) and BER of STX is under $1{\times}10^{-5}$ which meets the specification respectively. The FM STX is delivered Spacecraft Assembly, Integration and Test(AIT) level through the completion of functional Test and environmental(vibration, thermal vacuum) Test successfully.