• Title/Summary/Keyword: Interface Layer

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Buckling of an Orthotropic Layer Bonded to a Half-Space with an Interface Crack (계면균열을 갖는 반무한체에 접합된 직교이방성 층의 좌굴)

  • Jeong, Gyeong-Mun;Beom, Hyeon-Gyu
    • Journal of the Korean Society for Precision Engineering
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    • v.18 no.12
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    • pp.95-103
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    • 2001
  • The buckling of an orthotropic layer bonded to an orthotropic half-space with an interface crack subjected to compressive load under plane strain is analyzed. General solution to the stability equations describing the buckling behavior of both the layer and the half-space is expressed in terms of displacement functions. The displacement functions are represented by the solution of Cauchy-type singular integral equations, which are numerically solved. Numerical results of the critical buckling loads are presented fur various geometric parameters and material properties of both the layer and half-space.

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Effect of p-type a-SiO:H buffer layer at the interface of TCO and p-type layer in hydrogenated amorphous silicon solar cells

  • Kim, Youngkuk;Iftiquar, S.M.;Park, Jinjoo;Lee, Jeongchul;Yi, Junsin
    • Journal of Ceramic Processing Research
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    • v.13 no.spc2
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    • pp.336-340
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    • 2012
  • Wide band gap p-type hydrogenated amorphous silicon oxide (a-SiO:H) buffer layer has been used at the interface of transparent conductive oxide (TCO) and hydrogenated amorphous silicon (a-Si:H) p-type layer of a p-i-n type a-Si:H solar cell. Introduction of 5 nm thick buffer layer improves in blue response of the cell along with 0.5% enhancement of photovoltaic conversion efficiency (η). The cells with buffer layer show higher open circuit voltage (Voc), fill factor (FF), short circuit current density (Jsc) and improved blue response with respect to the cell without buffer layer.

Numerical Simulation of Effects of TGO Growth and Asperity Ratio on Residual Stress Distributions in TC-BC-TGO Interface Region for Thermal Barrier Coatings (열차폐 코팅의 TGO 성장과 형상비에 따른 TC-BC-TGO 계면에서의 잔류응력 변화에 대한 유한요소해석)

  • Jang, Jung-Chel;Choi, Sung-Churl
    • Journal of the Korean Ceramic Society
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    • v.43 no.7 s.290
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    • pp.415-420
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    • 2006
  • The residual stresses in the interface region of the Thermal Barrier Coating (TBC)/Thermally Grown Oxide (TGO)/Bond Coat (BC) were calculated on the TBC-coated superalloy samples using a Finite Element Method (FEM). It was found that the stress distribution of the interface boundary was dependent upon mainly the geometrical shape or its aspect ratio and the thickness of TGO layer, which was formed by growth and swelling behavior of oxide layer. Maximum compressive residual stress in the TBC/TGO interface is higher than that of the TGO/bond coat interface, and the tensile stress had nothing to do with change of an aspect ratio. The compressive residual stresses in the TBC/TGO and TGO/bond coat interface region increased gradually with the TGO growth.

Design of A 3.3V, 400 MBPS IEEE-1394 Physical Layer Transceiver (3.3V, 400MBPS IEEE-1394 물리층 트랜시버의 설계)

  • 황인철;한상찬송병준김수원
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.783-786
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    • 1998
  • We designed a 3.3 V, 400 Mbps IEEE-1394 physical layer transeiver on 0.6um 1P3M CMOS process. The transceiver drives a twisted pair cable of which differential impedance is 110 $\Omega$ so that differential amplitude reaches 200 mV at 400 Mbps and restores this small signal to rail-to-rail. Also, the transceiver arbitrates the interface among nodes on a bus configuration and supports both synchronous interface and asynchronous interface.

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Band Alignment at CdS/wide-band-gap Cu(In,Ga)Se2 Hetero-junction by using PES/IPES

  • Kong, Sok-Hyun;Kima, Kyung-Hwan
    • Transactions on Electrical and Electronic Materials
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    • v.6 no.5
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    • pp.229-232
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    • 2005
  • Direct characterization of band alignment at chemical bath deposition $(CBD)-CdS/Cu_{0.93}(In_{1-x}Ga_x)Se_2$ has been carried out by photoemission spectroscopy (PES) and inverse photoemission spectroscopy (IPES). Ar ion beam etching at the condition of the low ion kinetic energy of 400 eV yields a removal of surface contamination as well as successful development of intrinsic feature of each layer and the interfaces. Especially interior regions of the wide gap CIGS layers with a band gap of $1.4\~1.6\;eV$ were successfully exposed. IPES spectra revealed that conduction band offset (CBO) at the interface region over the wide gap CIGS of x = 0.60 and 0.75 was negative, where the conduction band minimum of CdS was lower than that of CIGS. It was also observed that an energy spacing between conduction band minimum (CBM) of CdS layer and valance band maximum (VBM) of $Cu_{0.93}(In_{0.25}Ga_{0.75})Se_2$ layer at interface region was no wider than that of the interface over the $Cu_{0.93}(In_{0.60}Ga_{0.40})Se_2$ layer.

Electrical Quadruple Layer under the AC Electric Field

  • Suh, Yong-Kweon
    • 한국전산유체공학회:학술대회논문집
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    • 2006.10a
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    • pp.167-176
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    • 2006
  • In this paper we show that solutions of the nonlinear Nernst-Planck equation possesses the quadruple-layer structure near the interface when the electrolyte receives a high frequency forcing such as a high-frequency alternating current. Very near to the interface wall, the well-known, classical Stern layer exists. Near to the Stern layer we have the secondly thin layer (to be called inner layer in this paper) where the ion concentrations behave under the same frequency as the external forcing. However, in this layer, the positive and negative ion concentrations develop with the time phase 180-degree different from each other. Next to this second layer, we have the third layer (called middle layer) in which two ion concentrations change with the time period double the forcing, and both concentrations behave in the same time phase. In the outermost layer, i.e. the forth layer, (called outer layer) the ion concentrations show the same-phase development as the third one but decaying very slowly in time. Our assertion is mostly based on the 1-D numerical simulation for the Nernst-Planck equation under a high frequency AC field assuming that the quadruple layer is very thin compared with the length scale representative of the bulk region.

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Influence of Thermal Aging at the Interface Cu/sn-Ag-Cu Solder Bump Made by Electroplating (전해도금에 의해 형성된 Sn-Ag-Cu 솔더범프와 Cu 계면에서의 열 시효의 영향)

  • Lee, Se-Hyeong;Sin, Ui-Seon;Lee, Chang-U;Kim, Jun-Gi;Kim, Jeong-Han
    • Proceedings of the KWS Conference
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    • 2007.11a
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    • pp.235-237
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    • 2007
  • In this paper, fabrication of Sn-3.0Ag-0.5Cu solder bumping having accurate composition and behavior of intermetallic compounds(IMCs) growth at interface between Sn-Ag-Cu bumps and Cu substrate were studied. The ternary alloy of the Sn-3.0Ag-0.5Cu solder was made by two binary(Sn-Cu, Sn-Ag) electroplating on Cu pad. For the manufacturing of the micro-bumps, photo-lithography and reflow process were carried out. After reflow process, the micro-bumps were aged at $150^{\circ}C$ during 1 hr to 500 hrs to observe behavior of IMCs growth at interface. As a different of Cu contents(0.5 or 2wt%) at Sn-Cu layer, behavior of IMCs was estimated. The interface were observed by FE-SEM and TEM for estimating of their each IMCs volume ratio and crystallographic-structure, respectively. From the results, it was found that the thickness of $Cu_3Sn$ layer formed at Sn-2.0Cu was thinner than the thickness of that layer be formed Sn-0.5Cu. After aging treatment $Cu_3Sn$ was formed at Sn-0.5Cu layer far thinner.

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A Design Of Physical Layer For OpenCable Copy Protection Module Using SystemC (SystemC를 이용한 OpenCableTM Copy Protection Module의 Physical Layer 설계)

  • Lee, Jung-Ho;Lee, Suk-Yun;Cho, Jun-Dong
    • Proceedings of the Korea Information Processing Society Conference
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    • 2004.05a
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    • pp.157-160
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    • 2004
  • 본 논문은 미국 차세대 디지털 케이블 방송 표준 규격인 오픈케이블($OpenCable^{TM}$)의 수신제한 모듈인 CableCard의 Physical Layer를 SystemC의 TLM(Transaction Level Modeling)과 RTL(Register-Transfer Level) 모델링 기법으로 설계하였다. 본 논문에서 설계한 CableCard의 Physical Layer는 PCMCIA Interface, Command Inteface 그리고 MPEG-2 TS Interface 로 구성된다. CableCard가 전원이 인가될 때, 카드 초기화를 위하여 동작하는 PCMCIA 인터페이스는 16 비트 PC 카드 SRAM 타입으로 2MByte Memory와 100ns access time으로 동작할 수 있게 설계하였다. PCMCIA 카드 초기화 동작이 완료된 후, CableCard의 기능을 수행하기 위하여 두 개의 논리적 인터페이스가 정의되는데 하나는 MPEG-2 TS 인터페이스이고, 다른 하나는 호스트(셋톱박스)와 모듈 사이의 명령어들을 전달하는 명령어 인터페이스(Command Interface)이다. 명령어 인터페이스(Command Interface)는 셋톱박스의 CPU와 통신하기 위한 1KByte의 Data Channel과 OOB(Out-Of-Band) 통신을 위한 4KByte의 Extended Channel 로 구성되고, 최대 20Mbits/s까지 동작한다. 그리고 MPEG-2 TS는 100Mbits/s까지 동작을 수행할 수 있게 설계하였다. 설계한 코드를 실행한 후, Cadence사의 SimVision을 통해서 타이밍 시뮬레이션을 검증하였다.

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Stabilizing Li2O-based Cathode/Electrolyte Interfaces through Succinonitrile Addition

  • Myeong Jun Joo;Yong Joon Park
    • Journal of Electrochemical Science and Technology
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    • v.14 no.3
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    • pp.231-242
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    • 2023
  • Li2O-based cathodes utilizing oxide-peroxide conversion are innovative next-generation cathodes that have the potential to surpass the capacity of current commercial cathodes. However, these cathodes are exposed to severe cathode-electrolyte side reactions owing to the formation of highly reactive superoxides (Ox-, 1 ≤ x < 2) from O2- ions in the Li2O structure during charging. Succinonitrile (SN) has been used as a stabilizer at the cathode/electrolyte interface to mitigate cathode-electrolyte side reactions. SN forms a protective layer through decomposition during cycling, potentially reducing unwanted side reactions at the interface. In this study, a composite of Li2O and Ni-embedded reduced graphene oxide (LNGO) was used as the Li2O-based cathode. The addition of SN effectively thinned the interfacial layer formed during cycling. The presence of a N-derived layer resulting from the decomposition of SN was observed after cycling, potentially suppressing the formation of undesirable reaction products and the growth of the interfacial layer. The cell with the SN additive exhibited an enhanced electrochemical performance, including increased usable capacity and improved cyclic performance. The results confirm that incorporating the SN additive effectively stabilizes the cathode-electrolyte interface in Li2O-based cathodes.