• 제목/요약/키워드: Interface Layer

검색결과 2,228건 처리시간 0.04초

MPLS모듈과 ATM모듈과의 Cell Mode 인터페이스를 위한 Multi-Port지원 UTOPIA-L2 Controller구현 (The Implementation of Multi-Port UTOPIA Level2 Controller for Interworking ATM Interface Module and MPLS Interface Module)

  • 김광옥;최병철;박완기
    • 한국통신학회논문지
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    • 제27권11C호
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    • pp.1164-1170
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    • 2002
  • ACE2000 MPLS시스템에서 MPLS 정합모듈은 ATM 정합모듈과 패킷 포워딩을 수행하는 HFMA(High performance Forwarding Engine and VC Merging board Assembly)모듈로 구성된다. MPLS 정합모듈에서 물리층으로 입력되는 셀은 HFMA의 송신 SAR칩(RSAR)에서 패킷으로 조립된 후 IP룩업 제어기에서 패킷 포워딩을 수행한다. 포워딩된 패킷은 ATM 계층으로 전달되기 위해 수신 SAR칩(TSAR)에서 셀로 다시 세그먼트된 후 ATM 셀 스위치로 전송하기 위해 ALMA(ATM Layer Module Assembly)로 전달된다. MPLS 정합모듈을 ATM 정합보듈로 이용할 때, ALMA는 직접 물리층 보드와 UTOPIA Leve12 인터페이스로 연결되며, 이때 ALMA는 Master Mode로 동작하게 된다 또한 MPLS 정합모듈에서 HFMA TSAR도 Master Mode로 동작하게 된다. 따라서 2개의 Master 모드 사이에서 인터페이스 역할을 수행할 수 있는 Slave 모드의 UTOPIA-L2 Controller가 요구된다. 본 논문에서는 Multi-Ports를 지원할 수 있는 UTOPIA-L2 Controller의 구조 및 셀 제어방법에 대해 고찰해본다.

Short channel SONOSFET 비휘발성 기억소자의 Si-$SiO_2$ 계면특성에 관한 연구 (A Study on the Characteristics of Si-$SiO_2$ interface in Short channel SONOSFET Nonvolatile Memories)

  • 김화목;이상배;서광열;강창수
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1993년도 하계학술대회 논문집 B
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    • pp.1268-1270
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    • 1993
  • In this study, the characteristics of Si-$SiO_2$ interface and its degradation in short channel SONOSFET nonvolatile memory devices, fabricated by 1Mbit CMOS process($1.2{\mu}m$ design rule), with $65{\AA}$ blocking oxide layer, $205{\AA}$ nitride layer, and $30{\AA}$ tunneling oxide layer on the silicon wafer were investigated using the charge pumping method. For investigating the Si-$SiO_2$ interface characteristics before and after write/erase cycling, charge pumping current characteristics with frequencies, write/erase cycles, as a parameters, were measured. As a result, average Si-$SiO_2$ interface trap density and mean value of capture cross section were determined to be $1.203{\times}10^{11}cm^{-2}eV^{-1}\;and\;2.091{\times}10^{16}cm^2$ before write/erase cycling, respectively. After cycling, when the write/erase cycles are $10^4$, average $Si-SiO_2$ interface trap density was $1.901{\times}10^{11}cm^{-2}eV^{-1}$. Incresing write/erase cycles beyond about $10^4$, Si-$SiO_2$ interface characteristics with write/erase cycles was increased logarithmically.

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Improved Efficiency by Insertion of TiO2 Interfacial Layer in the Bilayer Solar Cells

  • Xie, Lin;Yoon, Soyeon;Kim, Kyungkon
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2016년도 제50회 동계 정기학술대회 초록집
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    • pp.432.1-432.1
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    • 2016
  • We demonstrated that the power conversion efficiency (PCE) of bilayer solar cell was significantly enhanced by inserting interfacial layer between the organic bilayer film and the Al electrode. Moreover, the water contact angle shows that the bilayer solar cells suffer from the undesirable surface component which limits the charge transport to the Al electrode. The AFM measurement has revealed that the pre- and post-thermal annealing treatments results in different morphologies of the interfacial layer which is critical for the higher PCE of the bilayer solar cells. Furthermore we have investigated the electrical properties of the bilayer solar cells and obtained insights into the detailed device mechanisms. The transient photovoltage measurements suggests that the significantly enhanced Voc is caused by reducing the recombination at the interface between the organic films and the Al electrode. By inserting the TiO2 layer between the bilayer film and Al electrode, the open circuit voltage (Voc) was increased from 0.37 to 0.66V. Consequently, the power conversion efficiency (PCE) of bilayer solar cells was significantly enhanced from 1.23% to 3.71%. As the results, the TiO2 interfacial layer can be used to form an ohmic contact layer, serveing as a blocking layer to prevent the penetration of the Al, and to reduce the recombination at the interface.

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Monitoring of the Transfer of Tetrachloroaurate(III) Ions by Thin-layer Electrochemistry and Electrochemical Deposition of Metallic Gold over a Graphite Electrode

  • Song, Ji-Seon;Shin, Hyo-Sul;Kang, Chan
    • Bulletin of the Korean Chemical Society
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    • 제29권10호
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    • pp.1983-1987
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    • 2008
  • This study demonstrates the electrochemical conversion of the synthetic procedure of monolayer-protected clusters using a thin toluene layer over an edge plane pyrolytic graphite electrode. A thin toluene layer with a thickness of 0.31 mm was coated over the electrode and an immiscible liquid/liquid water/toluene interface was introduced. The transfer of the tetrachloroaurate ($AuCl_4^-$) ions into the toluene layer interposed between the aqueous solution and the electrode surface was electrochemically monitored. The $AuCl_4^-$ ions initially could not move through into the toluene layer, showing no reduction wave, but, in the presence of the phase transfer reagent, tetraoctylammonium bromide (TOABr), a cathodic wave at 0.23 V vs. Ag/AgCl was observed, indicating the reduction of the transferred $AuCl_4^-$ ions in the toluene layer. In the presence of dodecanethiol together with TOABr, a self-assembled monolayer was formed over the electro-deposited metallic gold surface. The E-SEM image of the surface indicates the formation of a highly porous metallic gold surface, rather than individual nanoparticles, over the EPG electrode.

Influence of KOH Solution on the Passivation of Al2O3 Grown by Atomic Layer Depostion on Silicon Solar Cell

  • 조영준;장효식
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2013년도 제45회 하계 정기학술대회 초록집
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    • pp.299.2-299.2
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    • 2013
  • We investigated the potassium remaining on a crystalline silicon solar cell after potassium hydroxide (KOH) etching and its effect on the lifetime of the solar cell. KOH etching is generally used to remove the saw damage caused by cutting a Si ingot; it can also be used to etch the rear side of a textured crystalline silicon solar cell before atomic layer-deposited Al2O3 growth. However, the potassium remaining after KOH etching is known to be detrimental to the efficiency of Si solar cells. In this study, we etched a crystalline silicon solar cell in three ways in order to determine the effect of the potassium remnant on the efficiency of Si solar cells. After KOH etching, KOH and tetramethylammonium hydroxide (TMAH) were used to etch the rear side of a crystalline silicon solar cell. To passivate the rear side, an Al2O3 layer was deposited by atomic layer deposition (ALD). After ALD Al2O3 growth on the KOH-etched Si surface, we measured the lifetime of the solar cell by quasi steady-state photoconductance (QSSPC, Sinton WCT-120) to analyze how effectively the Al2O3 layer passivated the interface of the Al2O3 layer and the Si surface. Secondary ion mass spectroscopy (SIMS) was also used to measure how much potassium remained on the surface of the Si wafer and at the interface of the Al2O3 layer and the Si surface after KOH etching and wet cleaning.

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카퍼 프탈로시아닌의 완충효과 (Buffer Effect of Copper Phthalocyanine(CuPC))

  • 김정현;신동명;손병청
    • 한국응용과학기술학회지
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    • 제16권4호
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    • pp.307-311
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    • 1999
  • Interfacial properties of electrode and organic thin layer is one of the most important factor in performing a Light Emitting Diodes(LED). Phthalocyanine copper was used as a buffer layer to improve interface characteristic, so that device efficiency was improved. In this study, LEDs were fabricated as like structures of Indium-Tin-Oxide (ITO) / N,N' -Diphenyl-N,N'-di(m-tolyl)-benzidine (TPD) / 8-Hydroxyquinoline aluminum(Alq) / Aluminum(Al) and Indium-Tin-Oxide(ITO) / N,N'-Diphenyl-N,N' -di(m-tolyl)-benzidine(TPD) / 2-(4-Biphenylyl)-5(4-tert-butyl-phenyl)-1,3,4-oxadiazole(PBD) / Aluminum(Al). In these devices, CuPC was layered at electrode/organic layer interface. As position is changing and thickness is changing, devices showed characteristic luminescence efficiency and luminescence inensity respectively. We showed in this study that luminescence efficiency was improved with CuPC layer in LEDs. The efficiency of device with layer CuPC is higher than that of 2 layer CuPC. However, the luminescence of 2 layer CuPC device got higher value.

압연 제조된 STS439/Al1050/ STS304 Clad소재의 열처리에 따른 계면 반응과 기계적 특성에서의 계면 반응 효과 (Interfacial Reaction on Heat Treatment of Roll-bonded STS304/Al1050/STS439 Clad Materials and its Effect on the Mechanical Properties)

  • 송준영;김인규;이영선;홍순익
    • 대한금속재료학회지
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    • 제49권11호
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    • pp.910-915
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    • 2011
  • The microstructures and mechanical properties of roll-bonded STS439/Al1050/STS304 clad materials were investigated after an annealing process at various temperatures. Interfacial layer was developed at the STS439/Al1050 and Al1050/STS304 interfaces at $550^{\circ}C$. STS439/Al1050/STS304 clad metals fractured suddenly in a single step and the fracture decreased with increasing annealing temperatures at $450^{\circ}C$. After annealing at $550^{\circ}C$, samples fractured in three steps with each layer fracturing independently. Interfacial layers formed at $550^{\circ}C$ with a high Vickers microhardness were found to be brittle. During tensile testing, periodic parallel cracks were observed at the interfacial reaction layer. Observed micro-void between Al1050 and the interfacial layer was found to weaken the Al1050/reaction layer interface, leading to the total separation between Al1050 and the reaction layer.

적층 구조를 적용한 용액 공정 IGZO 박막 트랜지스터의 특성 분석

  • 김현기;최병덕
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2015년도 제49회 하계 정기학술대회 초록집
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    • pp.212.1-212.1
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    • 2015
  • 본 연구에서는 용액 공정을 통해 제작한 IGZO 박막 트랜지스터의 Active layer를 적층 구조로 쌓아올리고, 신뢰성 평가를 위해 Gate에 지속적인 바이어스를 인가함으로써 소자의 문턱 전압 변화를 측정 실험을 진행하였다. Active layer 제작에 사용된 용액의 비율은 In:Zn:Ga = 1:1:30%로 제작되었고, 단일층부터 이중, 삼중층까지 적층을 하였다. 각 소자의 Active layer 층이 많아질수록 이동도가 1.21, 0.87, 0.69 ($cm^2/Vs$)으로 감소하는 등의 전기적 특성이 감소하는 경향을 보였다. 하지만 Gate에 10 V를 3000초간 지속적으로 인가해주었을 때 문턱 전압의 변화가 단일층일 때 10.4 V에서 삼중층일 때 1.3 V로 감소하였다. 이것은 Active layer의 층 사이의 계면이 형성되면서 current path에 영향을 주어 전기적 특성이 감소하였지만, 적층으로 인한 surface의 uniformity가 향상되는 것으로 확인하였다. 또한 1500초에서 Dit (Interface Trap Density)를 추출한 결과, 단일층에서는 $7.53{\times}10^{12}$($cm^{-2}-1$<)로 삼중층에서 $4.52{\times}10^{12}$($cm^{-2}-1$<)의 약 두 배 정도 높게 추출되었다.

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서비스 로봇용 결함 허용 미들웨어 (Fault-Tolerant Middleware for Service Robots)

  • 백범현;박홍성
    • 제어로봇시스템학회논문지
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    • 제14권4호
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    • pp.399-405
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    • 2008
  • Recently, robot technology is actively going on progress to the field of various services such as home care, medical care, entertainment, and etc. Because these service robots are in use nearby person, they need to be operated safely even though hardware and software faults occur. This paper proposes a Fault-Tolerant middleware for a robot system, which has following two characteristics: supporting of heterogeneous network interface and processing of software components and network faults. The Fault-Tolerant middleware consists of a Service Layer(SL), a Network Adaptation Layer(NAL), a Network Interface Layer(NIL), a Operating System ion Layer(OSAL), and a Fault-Tolerant Manager(FTM). Especially, the Fault-Tolerant Manager consists of 4 components: Monitor, Fault Detector, Fault Notifier, and Fault Recover to detect and recover the faults effectively. This paper implements and tests the proposed middleware. Some experiment results show that the proposed Fault-Tolerant middleware is working well.

계면균열을 가진 연성접합재의 소성영역 크기 - 이종 모재의 경우 - (Plastic Zone Size in a Ductile Layer with an Interface Crack - Case Study for Dissimilar Substrates -)

  • 김동학;강기주
    • 대한기계학회논문집A
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    • 제27권6호
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    • pp.898-904
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    • 2003
  • Using the modified Irwin model and the modified Dugdale model, the plastic zone size near the interface crack tip in a ductile layer bonding two dissimilar elastic substrates is predicted. Validity of the models is examined by finite element method. The effects of several factors such as the mode mixity, T-stress and material properties are explored. The plastic zone size significantly decreases with the Poisson's ratio of the ductile layer.