• Journal of Korea Multimedia Society
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• v.6 no.3
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• pp.556-564
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• 2003

A Star and Pancake graph also have such a good property of a hypercube and have a low network cost than the hypercube. A Macro-star graph which has the star graph as a basic module has the node symmetry, the maximum fault tolerance, and the hierarchical decomposition property. And, it is an interconnection network which improves the network cost against the Star graph. In this paper, we propose a method to embed between Star graph, Pancake graph, and Macro-star graph using the edge definition of graphs. We prove that the Star graph $S_n$ can be embedded into Pancake graph $P_n$ with dilation 4, and Macro-star graph MS(2,n) can be embedded into Pancake graph $P_{2n＋1}$ with dilation 4. Also, we have a result that the embedding cost, a Pancake graph can be embedded into Star and Macro-star graph, is O(n).

• The Journal of Korean Association of Computer Education
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• v.13 no.5
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• pp.91-102
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• 2010

Star graph is a well-known interconnection network to further improve the network cost of Hypercube and has good properties such as node symmetry, maximal fault tolerance and strongly hierarchical property. In this study, we will suggest embedding scheme among star graph and pancake graph, bubblesort graph, which are variations of star graph. We will show that bubblesort graph can be embedded into pancake and star graph with dilation 3, expansion 1, respectively and pancake graph can be embedded into bubblesort graph with dilation cost O($n^2$). Additionally, we will show that star graph can be embedded into pancake graph with dilation 4, expansion 1. Also, with dilation cost O(n) we will prove that star graph can be embedded into bubblesort graph and pancake graph can be embedded into star graph.

• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.65-72
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• 2019

HPC(High Performance Computing) is the computing system that connects a number of computing nodes with high performance interconnect network. In the HPC, interconnect network technology is one of the key player to make high performance systems, and mainly, Infiniband or Ethernet are used for interconnect network technology. Nowadays, PCIe interface is main interface within computer system in that host CPU connects high performance peripheral devices through PCIe bridge interface. For connecting between two computing nodes, PCIe Non-Transparent Bridge(NTB) standard can be used, however it basically connects only two hosts with its original standards. To give cost-effective interconnect network interface with PCIe technology, we develop a prototype of interconnect network system with PCIe NTB. In the prototyped system, computing nodes are connected to each other via PCIe NTB interface constructing switchless interconnect network such as ring network. Also, we have implemented prototyped data sharing mechanism on the prototyped interconnect network system. The designed PCIe NTB-based interconnect network system is cost-effective as well as it provides competitive data transferring bandwidth within the interconnect network.

• The KIPS Transactions:PartA
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• v.11A no.7 s.91
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• pp.499-510
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• 2004

This paper proposes a heuristic load balancing algorithm for multiprocessor systems. The algorithm minimizes the number of idle links to distribute load traffic and reduces its communication cost. Each processor iteratively tries to transfer unit load to/from every neighbor processors. However, real load transfer is collectively done after complete load traffic calculation to minimize useless traffic. The proposed algorithm can be employed in various interconnection topologies with slight modifications. In this paper, it is applied to both hypercube and mesh environments. For performance evaluation, simulation studies are performed. The performance of proposed algorithm is compared to those of two well-known algorithms. The results show that the proposed algorithm always balances the loads perfectly. Furthermore, it reduces the communication costs by $70{\%}{\~}90{\%}$ in the hypercube ; and it reduces the cost by $\75{\%}$ in the mesh, compared to existing algorithms.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.1
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• pp.82-92
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• 2000

This paper introduces an implementation of the diagnosis software for CC-NUMA systems. The CC-NUMA architecture is composed of two or more SMP nodes installed with the specialized hardware to provide cache-coherent operation and the high-speed interconnection network to connect each node, it enables both the high performance and the high scalability. While the CC-NUMA system provides the single system image in the operating system aspect, it should be considered the multiple systems by the diagnostic software. Thus it is difficult to diagnose and manage CC-NUMA system using commercial administration software due to characteristics of the complicated architecture. The remote diagnosis and management are also required with a view to reduce Total Cost of Ownership. In this paper, we design diagnostic software to manage CC-NUMA server system, and propose its mechanism in client-server manner to support remote administration. Additionally, we use the Java-based user interface to enlarge an administrator's accessibility.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.22 no.12
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• pp.1667-1674
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• 2018

Recently, speeding up real time calculation using the specialized hardware accelerator is often used in the various engineering and science area, and the accelerators are required to include PCI express interconnection between FPGA and a host computer. The implementation of the high speed PCIe for the multi-giga bytes per second transmission is one of the most difficult issue in the development of the accelerators. There are several commercialized IP solutions and research results in the literature, but these solutions are required extra cost and design period to analyze the detailed implementation method. For the hardware accelerator on Xilinx FPGA, utilizing Xilinx's XDMA PCIe IP, which is provided without extra charge, can be the best solution in terms of the development period and cost. Consequently, this paper presents the evaluation system on Zynq-7000 FPGA and Windows 10 host computer, and analyze the performance of the PCIe IP with various configuration parameters.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.1
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• pp.3-6
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• 2015

Recently, the collection of the sensor data and its analysis become important as the smart buildings equipped with the various sensors appear as a usual scene. The interconnection through the wire cable among the sensors is indispensible because of the information collections such as the temperature, the humidity, and the luminance in the rooms and the hallways for the effective management of the in-building energies. However, these interconnections through the cabling will be very costly, time-consuming, and a difficult task since they will cause some damages to the buildings. Therefore, the interconnections through the unwired connections are required in terms of the deployment effectiveness such as time and cost In this paper, the design and the operation appropriateness are confirmed through the simulation of the signal measurement system for in-building propagation characteristics based on signature sequence.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.54 no.10
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• pp.615-619
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• 2005

Token coherence protocol has many good reasons against snooping/directory-based protocol in terms of latency, bandwidth, and complexity. Token counting easily maintains correctness of the protocol without global ordering of request which is basis of other dominant cache coherence protocols. But this lack of global ordering causes starvation which is not happening in snooping/directory-based protocols. Token coherence protocol solves this problem by providing an emergency mechanism called persistent request. It enforces other processors in the competition (or accessing same shared memory block, to give up their tokens to feed a starving processor. However, as the number of processors grows in a system, the frequency of starvation occurrence increases. In other words, the situation where persistent request occurs becomes too frequent to be emergent. As the frequency of persistent requests increases, not only the cost of each persistent matters since it is based on broadcasting to all processors, but also the increased traffic of persistent requests will saturate the bandwidth of multiprocessor interconnection network. This paper proposes a new request mechanism that defines order of requests to reduce occurrence of persistent requests. This ordering mechanism has been designed to be decentralized since centralized mechanism in both snooping-based protocol and directory-based protocol is one of primary reasons why token coherence protocol has advantage in terms of latency and bandwidth against these two dominant Protocols.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.11a
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• pp.53-58
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• 2003

The Wafer Level Packaging is one of the most important technologies in the semiconductor industry today. Its primary advantages are its small form factor and low cost potential for manufacturing including test procedure. The CASIO's WLP samples, application example and the structure are shown in Fig.1, 2&3. There are dielectric layer , under bump metal, re-distribution layer, copper post , encapsulation material and terminal solder .The key technologies are 'Electroplating thick copper process' and 'Unique wafer encapsulation process'. These are very effective in getting electrical and mechanical advantages of package. (Fig. 4). CASIO and CMK are developing a new System Packaging technology called the Embedded Wafer Level Package (EWLP) together. The active components (semiconductor chip) in the WLP structure are embedded into the Printed Wiring Board during their manufacturing process. This new technical approach has many advantages that can respond to requirements for future mobile products. The unique feature of this EWLP technology is that it doesn't contain any solder interconnection inside. In addition to improved electrical performance, EWLP can enable the improvement of module reliability. (Fig.5) The CASIO's WLP Technology will become the effective solution of 'KGD problem in System Packaging'. (Fig. 6) The EWLP sample shown in Fig.7 including three chips in the WLP form has almost same structure wi_th SoC's. Also, this module technology are suitable for RF and Analog system applications. (Fig. 8)

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1996.11a
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• pp.291-294
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• 1996

We present the experimental results of high quality factor (Q) inductors fabricated on high-resistivity silicon wafer using standard CMOS process without any modificatons such as thick gold layer or multilayer interconnection. This demonstrates the possibility of building high Q inductors using lower cost technologies, compared with previous results using complicated process. The comparative analysis is carried out to find the optimized inductor shape for the maximum performance by varying the thickness of metal and number of turns with rectangular shape.