• Journal of Communications and Networks
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• v.14 no.2
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• pp.213-221
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• 2012

The architecture of an interconnection network is usually represented by a graph, and a graph G is bipancyclic if it contains a cycle for every even length from 4 to ${\mid}V(G){\mid}$. In this article, we analyze the conditional edge-fault-tolerant properties of an enhanced hypercube, which is an attractive variant of a hypercube that can be obtained by adding some complementary edges. For any n-dimensional enhanced hypercube with at most (2n-3) faulty edges in which each vertex is incident with at least two fault-free edges, we showed that there exists a fault-free cycle for every even length from 4 to $2^n$ when n($n{\geq}3$) and k have the same parity. We also show that a fault-free cycle for every odd length exists from n-k+2 to $2^n-1$ when n($n{\geq}2$) and k have the different parity.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1401-1411
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• 1999

Due to the increase of multimedia services, multicasting is considered as important design factor for ATM switch. To resolve the traffic expansion problem that is occurred by multicast in multistage interconnection networks, this paper proposes the multicast switch using a high-speed bus and a shared memory switch. Since the proposed switch uses a high-speed time division bus as a connection medium and chooses a shared memory switch as a basic switch module, it provides good port scalability. The traffic arbitration scheme enables internal non-blocking. By simulation we proves a good performance in the data throughput and the cell delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.11B
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• pp.946-955
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• 2004

It is shown that the do Bruijn graph (dBG) can be used as an architecture for interconnection network and a suitable structure for parallel computation. Recent works have classified dBG based routing algorithms into shortest path routing and fault tolerant routing but investigation into fault free shortest path (FFSP) on dBG has been non-existent. In addition, as the size of the network increase, more faults are to be expected and therefore shortest path dBG algorithms in fault free mode may not be suitable routing algorithms for real interconnection networks, which contain several failures. Furthermore, long fault free path may lead to high traffic, high delay time and low throughput. In this paper we investigate routing algorithms in the condition of existing failure, based on the Bidirectional do Bruijn graph (BdBG). Two FFSP routing algorithms are proposed. Then, the performances of the two algorithms are analyzed in terms of mean path lengths and discrete set mean sizes. Our study shows that the proposed algorithms can be one of the candidates for routing in real interconnection networks based on dBG.

• Journal of the Korea Society of Computer and Information
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• v.15 no.11
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• pp.1-9
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• 2010

As the process technology scales down, an interconnection has became a major performance constraint for multi-core processors. Recently, in order to mitigate the performance bottleneck of the interconnection for multi-core processors, a 3D integration technique has drawn quite attention. The 3D integrated multi-core processor has advantage for reducing global wire length, resulting in a performance improvement. However, it causes serious thermal problems due to increased power density. For this reason, to design efficient 3D multi-core processors, thermal-aware design techniques should be considered. In this paper, we analyze the temperature on the 3D multi-core processors in function unit level through various experiments. We also present temperature characteristics by varying application features, cooling characteristics, and frequency levels on 3D multi-core processors. According to our experimental results, following two rules should be obeyed for thermal-aware 3D processor design. First, to optimize the thermal profile of cores, the core with higher cooling efficiency should be clocked at a higher frequency. Second, to lower the temperature of cores, a workload with higher thermal impact should be assigned to the core with higher cooling efficiency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.12
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• pp.45-52
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• 2005

A systolic array formed by interconnecting a set of identical data-processing cells in a uniform manner is a combination of an algorithm and a circuit that implements it, and is closely related conceptually to arithmetic pipeline. High-performance computation on a large array of cells has been an important feature of systolic array. To achieve even higher degree of concurrency, it is desirable to make cells of systolic array themselves systolic array as well. The structure of systolic array with its cells consisting of another systolic array is to be called super-systolic array. This paper proposes a scalable bit-level super-systolic amy which can be adopted in the VLSI design including regular interconnection and functional primitives that are typical for a systolic architecture. This architecture is focused on highly regular computational structures that avoids the need for a large number of global interconnection required in general VLSI implementation. A bit-level super-systolic FIR filter is selected as an example of bit-level super-systolic array. The derived bit-level super-systolic FIR filter has been modeled and simulated in RT level using VHDL, then synthesized using Synopsys Design Compiler based on Hynix $0.35{\mu}m$ cell library. Compared conventional word-level systolic array, the newly proposed bit-level super-systolic arrays are efficient when it comes to area and throughput.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.24-31
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• 2007

Up to date, a lot of bus protocol and bus architecture are released though most of them are based on the shared bus architecture and inherit the limitation of performance. SNP (SoC Network Protocol), and hence, SNA (SoC Network Architecture) which are high performance on-chip-bus protocol and architecture, respectively, have been proposed to solve the problems of the conventional shared bus. We refine the SNA specification and improve the performance and functionality. The performance of the SNA is improved by supporting simultaneous routing for bus request of multiple masters. The internal routing logic is also improved so that the gate count is decreased. The proposed SNA employs XSNP (extended SNP) that supports almost perfect compatibility with AMBA AHB protocol without performance degradation. The hardware complexity of the improved SNA is not increased much by optimizing the current routing logic. The improved SNA works for IPs with the original SNP at its best performance. In addition, it can also replace the AMBA AHB or interconnect matrix of a system, and it guarantees simultaneous multiple channels. That is, the existing AMBA system can show much improved performance by replacing the AHB or the interconnect matrix with the SNA. Thanks to the small number of interconnection wires, the SNA can be used for the off-chip bus system, too. We verify the performance and function of the proposed SNA and XSNP simulation and emulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.131-139
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• 2013

To overcome the limitations in performance and power consumption of traditional electrical interconnection based network-on-chips (NoCs), a hybrid optical network-on-chip (HONoC) architecture using optical interconnects is emerging. However, the HONoC architecture should use circuit-switching scheme owing to the overhead by optical devices, which worsens the latency unfairness problem caused by frequent path collisions. This resultingly exert a bad influence in overall performance of the system. In this paper, we propose a new task mapping algorithm for optimizing latency by reducing path collisions. The proposed algorithm allocates a task to a certain processing element (PE) for the purpose of minimizing path collisions and worst case latencies. Compared to the random mapping technique and the bandwidth-constrained mapping technique, simulation results show the reduction in latency by 43% and 61% in average for each $4{\times}4$ and $8{\times}8$ mesh topology, respectively.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.12
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• pp.2340-2352
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• 1994

Under the current IN(Intelligent Network) Architecture, most of their function were performed in SSP(Service Switching point), so the provision or modification of service was limited. To over come these limitation, the structure of 'AIN(Advanced Intelligent Network)' emerged. In this paper, SSP for AIN structure is designed and its performance is evaluated. In other words, the requirements for AIN service implementation are specified on the basis of ITU-T Recommendations. From these requirments and TDX-10 Exchange architecture, the SSP for AIN structure is designed, and its performance is analyzed through the method of simulation and analytical modeling. As a conclusion of this paper, when the system is operated as a standard model, the maximum throughput is 1,270,000 BHCA for Free Phone Service and 1,190,000 BHCA for Credit Call Service. The processors in INS(Interconnection Network Subsystem) are proved to be bottleneck elements. To enhance the performance, several suggestions such as processor and link speedup, and other D_bus service policy are proposed.

• Journal of the Korean Institute of Landscape Architecture International Edition
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• no.1
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• pp.176-182
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• 2001

The case for study in this paper is the Main Plan and Management for the Fukutoshin; the restructure of Nishi Shinjuku, This plan was first outlines in 1960, and includes a vast area of 96 ha for redevelopment. It aims to create a totally new center in the city. This was the first case in Japan, and in the world of a plan of these magnitudes. involving urban landscape restructuring from three points: Landscape (open spaces for public use: the Shinjuku Central Park and the surrounding area of the buildings), transport and commercial building developments. The Landscape plan for the green areas was decided in a way to compensate the population of the area and the visitors. As a rule, high-rise building constructions are placed each one in single lots and are surrounded by open spaces and greenery. Pedestrain areas are widened and also connected by bridges in a way to allow free circulation, and interconnection between the constructions and the green areas. Another important factor is the role that Private Corporation, and public interest plays. Joining these two forces has allowed the concretization of this project. This interpolation between public and private roles was an innovation in Japan, and it also the key for the concretion of the project. The historical review of the process and management of this project help us to put into perspective the introduction of new concepts and ideas, which were not related at that time to traditional Japanese Landscaping. Furthermore we are better able to understand the substantial increase in the percentage of land dedicated to green areas in contrast to the typical standards of Japanese cities.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.1
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• pp.82-92
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• 2000

This paper introduces an implementation of the diagnosis software for CC-NUMA systems. The CC-NUMA architecture is composed of two or more SMP nodes installed with the specialized hardware to provide cache-coherent operation and the high-speed interconnection network to connect each node, it enables both the high performance and the high scalability. While the CC-NUMA system provides the single system image in the operating system aspect, it should be considered the multiple systems by the diagnostic software. Thus it is difficult to diagnose and manage CC-NUMA system using commercial administration software due to characteristics of the complicated architecture. The remote diagnosis and management are also required with a view to reduce Total Cost of Ownership. In this paper, we design diagnostic software to manage CC-NUMA server system, and propose its mechanism in client-server manner to support remote administration. Additionally, we use the Java-based user interface to enlarge an administrator's accessibility.