• Journal of the Korean Institute of Telematics and Electronics A
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• v.32A no.8
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• pp.19-30
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• 1995

For the efficient interconnection between SMDS and LAN, an interconnection protocol architecture in the router is proposed in this paper. A control method of xongestion which is produced by this interconnection of SMDS and LAN is also proposed. Especially, the SIP level 3 of SMDS is devided into CS-SIP3 sublayer and CLNAP sublayer in order to circumvent the problems which are producted by the protocol difference of two networks and to consider the interconnection with B-ISDN in the future. In this way, the interconnection of SMDS and LAN is transparentlly achieved through CLNAP layer, and the interconnection protocol architecture becomes simple. To test the performance of the router, amodel of interconnection protocol which is proposed by this paper is simulated using sliding window flow control. The simulation results show that the throughput of router is increased. The packet delay and the rate of packet discard are also decreased.

• Proceedings of the IEEK Conference
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• 2003.07b
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• pp.823-826
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• 2003

FPGA-based logic emulator with lane gate capacity generally comprises a large number of FPGAs connected in mesh or crossbar topology. However, gate utilization of FPGAs and speed of emulation are limited by the number of signal pins among FPGAs and the interconnection architecture of the logic emulator. The time-multiplexing of interconnection wires is required for multi-FPGA system incorporating several state-of-the-art FPGAs. This paper proposes a circuit partitioning algorithm called SCATOMi(SCheduling driven Algorithm for TOMi)for multi-FPGA system incorporating four to eight FPGAs where FPGAs are interconnected through TOMi(Time-multiplexed, Off-chip, Multicasting interconnection). SCATOMi improves the performance of TOMi architecture by limiting the number of inter-FPGA signal transfers on the critical path and considering the scheduling of inter-FPGA signal transfers. The performance of the partitioning result of SCATOMi is 5.5 times faster than traditional partitioning algorithms. Architecture comparison show that the pin count is reduced to 15.2%-81.3% while the critical path delay is reduced to 46.1%-67.6% compared to traditional architectures.

• Journal of Power Electronics
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• v.10 no.1
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• pp.97-105
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• 2010

This paper presents the modeling, control and simulation of an interconnection system (ICS) of cascaded distributed generation (DG) modules for both grid-tied and stand-alone operations. The overall configuration of the interconnection system is given. The interconnection system consists of a cascaded DC/DC boost converters and a DC/AC inverter. Detailed modeling of the interconnection system incorporating a cascaded architecture has not been considered in previous research. In this paper, suitable control systems for the cascaded architecture of power electronic converters in an interconnection system have been studied and modeled in detail. A novel control system for DC/DC boost converters is presented based on a droop voltage controller. Also, a novel control strategy for DC/AC inverters based on the average large signal model to control the aggregated DG modules under both grid-tied and stand-alone modes is demonstrated. Simulation results indicate the effectiveness of the proposed control systems.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.1
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• pp.94-101
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• 2010

Optimization of interconnects among processors and memories becomes important as multiple processors and memories can be integrated on a Multi-Processor System-on-Chip (MPSoC). Since the optimal interconnection architecture is usually dependent on the applications, systematic design methodology for various data transfer requirements is necessary. In this paper, we focus on bus interconnection for MPSoC applications which use 4 ~ 16 processors. We propose a new systematic bus design methodology under performance constraints using Single Arbitration Multiple Bus Accesses (SAMBA) style bus architectures. Optimized bus architecture is found to satisfy performance constraints for a single or multiple applications. When compared to the unoptimized architecture, our method can reduce the bus switch logic circuits significantly (by more than 50% sometimes). Furthermore, low cost bus architectures can be found to satisfy the performance constraints for multiple applications.

• Journal of KIISE:Computer Systems and Theory
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• v.34 no.12
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• pp.656-664
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• 2007

Field-Programmable Gate Arrays (FPGAs) are a revolutionary new type of user-programmable integrated circuits that provide fast, inexpensive access to customized VLSI. However, as the target application speed increases, power-consumption and wire-delay on interconnection become more critical factors during programming an FPGA. Especially, the interconnection of the FPGA consumes 65% of the total FPGA power consumption. A previous research show that if the length of interconnection is shirked, power-consumption can be reduced because an interconnection has a lot of effect on power-consumption. For solving this problem that reducing the number of wires routed, the three dimension FPGA is proposed. However, this structure physical wires and an area of switches is increased by making topology complex. This paper propose a novel FPGA architecture that modifies the three dimension FPGA and compare the number of interconnection of Virtex II and 3D FPGA with the proposed FPGA architecture using the FPGA Editor of Xilinx ISE and a global routing and length estimation program.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.10
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• pp.57-66
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• 2010

Today the various types of communication and application service are provided by the development of Internet and IP technologies. It is expected to be extended the service domain of two networks through the interconnecting P2PSIP overlay which is highlighted as an important technologies for Internet based services and IMS(IP Multimedia Subsystem) which is the new architecture adopted in the evolution of NGN. Therefore, this paper explains the possible methods of the service expansion with interconnecting P2PSIP overlay and IMS network. Specially this paper suggests the interconnection architectures of P2PSIP overlay and IMS network as subscriber's types and analyzes the traffic analysis model and session set up delay characteristics by simulation model. As a results, this paper shows that the interconnection architecture using gateway AS(Application Server) is the excellent method to interconnect the IMS in case of P2PSIP overlay only subscriber, and that interconnection architecture using I-CSCF is good method to interconnect the IMS in case of P2PSIP overlay and IMS subscriber.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.4
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• pp.318-328
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• 2011

Stage-level reconfigurable chip multiprocessor (CMP) aims to achieve highly reliable and fault tolerant computing by using interwoven pipeline stages and on-chip interconnect for communicating with each other. The existing crossbar-switch based stage-level reconfigurable CMPs offer high reliability at the cost of significant area/power overheads. These overheads make realizing large CMPs prohibitive due to the area and power consumed by heavy interconnection networks. On other hand, area/power-efficient architectures offer less reliability and inefficient stage-level resource utilization. In this paper, I propose a hierarchical multiplexing interconnection structure in lieu of crossbar interconnect to design area/power-efficient stage-level reconfigurable CMP. The proposed approach is able to keep the reliability offered by the crossbar-switch while reducing the area and power overheads. Experimental results show that the proposed approach reduces area by up to 21% and power by up to 32% when compared with the crossbar-switch based interconnection network.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.8
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• pp.33-44
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• 2011

In this paper, we presents a hybrid on-chip bus architecture based on the AMBA 3.0 AXI protocol for MPSoC with high performance and low power. Among AXI channels, data channels with a lot of traffic are designed by crossbar-switch architecture for massively parallel processing. On the other hand, addressing and write-response channels having a few of traffic is handled by shared-bus architecture due to the overheads of (areas, interconnection wires and power consumption) reduction. In experiments, the comparisons are carried out in terms of time, space and power domains for the verification of proposed hybrid on-chip bus architecture. For $16{\times}16$ bus configuration, the hybrid on-chip bus architecture has almost similar performance in time domain with respect to crossbar on-chip bus architecture, as the masters's latency is differenced about 9% and the total execution time is only about 4%. Furthermore, the hybrid on-chip bus architecture is very effective on the overhead reduction, such as it reduced about 47% of areas, and about 52% of interconnection wires, as well as about 66% of dynamic power consumption. Thus, the presented hybrid on-chip bus architecture is shown to be very effective for the MPSoC interconnection design aiming at high performance and low power.

• Journal of Information Technology Services
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• v.7 no.1
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• pp.131-149
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• 2008

Bandwidth Trading(BT) represents a potential market with over 1 trillion USD across the world and high growth potential. BT is also likely to accelerate globalization of the telecommunications industry and massive restructuring driven by unbundling rush. However, systematic researches on BT remain at an infant stage. This study starts with structure analysis of the Internet industry, and discusses significance of Internet interconnection with respect to BT Issues. We also describe the bandwidth commoditization trends and review technical requirements for effective Internet interconnection with BT capability. Taking a step further, this study explores the possibility of improving efficiency of network providers and increasing user convenience by developing an architectural prototype of Hub-&-Spoke interconnection model required to facilitate BT. The BT market provides an Innovative base to ease rigidity of two-party contract and Increase service efficiency. However, as fair, efficient operation by third party is required, this research finally proposes an exchanging hub named NIBX(New Internet Business eXchange).

• Journal of information and communication convergence engineering
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• v.20 no.3
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• pp.160-165
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• 2022

This paper proposes an efficient method of reconstructing interconnections when the terminals of each plane change in real-time situations where randomly divided planes are interconnected. To connect all terminals when the terminals of each plane are changed, we usually reconstruct the interconnections between all terminals. This ensures a minimum connection length, but it takes considerable time to reconstruct the interconnection for the entire terminal. This paper proposes a solution to obtain an optimal tree close to the minimum spanning tree (MST) in a short time. The construction of interconnections has been used in various design-related areas, from networks to architecture. One of these areas is an ad hoc network that only consists of mobile hosts and communicates with each other without a fixed wired network. Each host of an ad hoc network may appear or disappear frequently. Therefore, the heuristic proposed in this paper may expect various cost savings through faster interconnection reconstruction using the given information in situations where the connection target is changing.