• 방송공학회논문지
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• 제23권5호
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• pp.606-613
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• 2018

본 연구는 대규모 영상처리를 위한 메모리 확장을 위한 외장 메모리 확장장치 구현에 관련된 내용으로, 이는 영상처리를 위한 그래픽 워크스테이션에 장착되는 PCI(Peripheral Component Interconnect) Express Gen3 x8 인터페이스를 가지는 외장 메모리 어댑터 카드와 외장 DDR(Dual Data Rate) 메모리로 구성된 외장 메모리 보드로 구성되며, 메모리 어댑터 카드와 외장 메모리 보드간의 연결은 광 인터페이스를 통하여 이루어진다. 외장 메모리 억세스를 위해서는 Programmable I/O 방식과 DMA(Direct Memory Access) 방식을 모두 사용할 수 있도록 하여 영상 데이터의 효율적 송수신이 이루어지도록 하였다. 본 연구 결과의 구현은 Altera Stratix V FPGA(Field Programmable Gate Array)와 40G 광 트랜시버가 장착된 보드를 사용하였으며, 1.6GB/s의 대역폭 성능을 보여주고 있다. 이는 4K UHD(Ultra High Definition) 영상 한 채널을 담당할 수 있는 규모이다. 향후 본 연구를 계속 진행하여 3GB/s 이상 대역폭을 보이는 연구결과를 보일 예정이다.

• 한국태양에너지학회 논문집
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• 제38권1호
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• pp.45-55
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• 2018

Environmentally benign lead-free solder coated ribbon (e. g. SnCu, SnZn, SnBi${\cdots}$) has been intensively studied to interconnect cells without lead mixed ribbon (e. g. SnPb) in the crystalline silicon(c-Si) photovoltaic modules. However, high melting point (> $200^{\circ}C$) of non-lead based solder provokes increased thermo-mechanical stress during its soldering process, which causes early degradation of PV module with it. Hence, we proposed low-temperature conductive paste (CP) based tabbing method for lead-free ribbon. Modules, interconnected by the lead-free solder (SnCu) employing CP approach, exhibits similar output without increased resistivity losses at initial condition, in comparison with traditional high temperature soldering method. Moreover, 400 cycles (2,000 hour) of thermal cycle test reveals that the module integrated by CP approach withstands thermo-mechanical stress. Furthermore, this approach guarantees strong mechanical adhesion (peel strength of ~ 2 N) between cell and lead-free ribbons. Therefore, the CP based tabbing process for lead free ribbons enables to interconnect cells in c-Si PV module, without deteriorating its performance.

• Design & Manufacturing
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• 제6권1호
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• pp.95-100
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• 2012

In this study, a novel Cu composite sheet with embedded high electric conduction path was developed as another alternative for the interconnect materials possessing high electrical conductivity as well as high strength. The Cu composite sheet was fabricated by forming Ag conduction paths not within the interior but on the surface of a high strength Cu substrate by damascene electroplating process. As a result, the electrical conductivity increased by 40% thanks to mesh type Ag conduction paths, while the ultimate tensile strength decreased by 20%. The interfacial fracture resistance of Cu composite sheet prepared by damascene electroplating increased by above 50 times compared to Cu composite sheet by conventional electroplating. For feasibility test for practical application, a leadframe for LED module was manufactured by a progressive blanking and piercing processes, and the blanked surface profile was evaluated as a function of the volume fraction of Ag conduction paths. As Ag conduction path became finer, pressing formability improved.

• 한국경영과학회지
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• 제30권4호
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• pp.151-161
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• 2005

For Internet service providers (ISPs), there are three common types of interconnection agreements : private peering, public peering and transit. One of the most important problems for a single ISP is to determine which other ISPs to interconnect with, and under which agreements. The problem can be then to find a set of private peering providers, transit providers and Internet exchanges (IXs) when the following input data are assumed to be given : a set of BGP addresses with traffic demands, and a set of potential service providers (Private peering/transit providers and IXs) with routing information, cost functions and capacities. The objective is to minimize the total interconnection cost. We show that the problem is NP-hard, give a mixed-integer programming model, and propose a heuristic algorithm. Computational experience with a set of test instances shows the remarkable performance of the proposed algorithm of rapidly generating near-optimal solutions.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2002년도 하계학술대회 논문집
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• pp.18-21
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• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher due to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method is applied with the rule based optical proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design nile is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 하계종합학술대회 논문집(2)
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• pp.209-212
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• 2002

As the mask design rules get smaller, the probability of the process failure becomes higher doc to the narrow overlay margin between the contact and metal interconnect layers. To obtain the minimum process margin, a tabbing and cutting method Is applied with the rule based optical\ulcorner proximity correction to the metal layer, so that the protection to bridge problems caused by the insufficient space margin between the metal layers can be accomplished. The side-lobe phenomenon from the attenuated phase shift mask with the tight design rule is analyzed through the aerial image simulation for test patterns with variation of the process parameters such as numerical aperture, transmission rate, and partial coherence. The corrected patterns are finally generated by the rules extracted from the side-lobe simulation.

• 대한전자공학회논문지SD
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• 제39권1호
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• pp.67-75
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• 2002

본 논문에서는 대략적인 PEEC 방법에 대해 논의 하고, 도선에 대하여 PEEC 등가회로를 구성하였으며, 주어진 등가회로로 부터 시스템의 행렬을 구하고, 이 행렬을 수치 해석적인 방법을 이용한 시뮬레이션을 수행하여 노드에서의 전압과 전류를 구하였다. PEEC 등가 회로를 구성하기 위해서, PEEC 등가 회로를 구성하는 성분(R, L, C)을 유한 요소법(finite element method)을 이용한 시뮬레이터를 이용하여 추출하였으며, 생성된 등가 회로에 대한 과도 해석을 수행하였다.

• Journal of Welding and Joining
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• 제32권3호
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• pp.53-59
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• 2014

The mechanical stability of solder joints in electronic devices with Sn-Ag-Cu is a continuous issue since the material was applied to the industry. Various shock test methods were developed and standardized tests are used in the industry worldwide. Although it is applied for several years, the detailed mechanism of the shock induced failure mechanism is still under investigation. In this study, the effect of external temperature was observed on large Flip-chip BGA components. The weight and size of the large package produced a high strain region near the corner of the component and thus show full fracture at around 200G level shock input. The shock performance at elevated temperature, at $100^{\circ}C$ showed degradation based on board pad designs. The failure mode and potential failure mechanisms are discussed.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제49권8호
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• pp.433-437
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• 2000

We fabricated switch module of ATM(Asynchronous Transfer Mode) exchange system with MCM-C(MultiChip Module Co-fired) technology and measured its electrical characteristics. Green tape was used as substrate and Au/Ag paste was used to form the interconnect layers. The via holes were made by drill and filled with metal paste usign screen method. After manufacturing the substrate, chips and passive components were assembled on the substrate. In electrical test, the module showed the output signal of 46.9MHz synchronized with input signal. In the view of substrate size reduction, the area of MCM switch module was 35% of conventional hybrid switch module.

• 전자공학회논문지C
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• 제34C권2호
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• pp.38-49
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• 1997

In this paper, w describe partitioning large circuits into multiple chips on the programmable FPCB for rapid prototyping. FPCBs consists of areas for FPGAs for logic and interconnect components, and the routing topology among them are predetermined. In the partition problem for FPCBs, the number of wires ofr routing among chips is fixed, which is an additonal constraints to the conventional partition problem. In order to deal with such aconstraint properly we first define a new partition problem, so called the topologybased partition problem, and then propose a heuristic method. The heuristic method is based on the simulated annealing and clustering technique. The multi-level tree clustering technique is used to obtain faster and better prtition results. In the experimental results for several test circuits, the restrictions for FPCB were all satisfied and the needed execution time was about twice the modified K-way partition method for large circuits.