• KIPS Transactions on Computer and Communication Systems
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• v.8 no.3
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• pp.65-72
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• 2019

HPC(High Performance Computing) is the computing system that connects a number of computing nodes with high performance interconnect network. In the HPC, interconnect network technology is one of the key player to make high performance systems, and mainly, Infiniband or Ethernet are used for interconnect network technology. Nowadays, PCIe interface is main interface within computer system in that host CPU connects high performance peripheral devices through PCIe bridge interface. For connecting between two computing nodes, PCIe Non-Transparent Bridge(NTB) standard can be used, however it basically connects only two hosts with its original standards. To give cost-effective interconnect network interface with PCIe technology, we develop a prototype of interconnect network system with PCIe NTB. In the prototyped system, computing nodes are connected to each other via PCIe NTB interface constructing switchless interconnect network such as ring network. Also, we have implemented prototyped data sharing mechanism on the prototyped interconnect network system. The designed PCIe NTB-based interconnect network system is cost-effective as well as it provides competitive data transferring bandwidth within the interconnect network.

• Journal of Information Processing Systems
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• v.18 no.1
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• pp.159-172
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• 2022

The role of the interconnect network, which connects computing nodes to each other, is important in high-performance computing (HPC) systems. In recent years, the peripheral component interconnect express (PCIe) has become a promising interface as an interconnection network for high-performance and cost-effective HPC systems having the features of non-transparent bridge (NTB) technologies. OpenSHMEM is a programming model for distributed shared memory that supports a partitioned global address space (PGAS). Currently, little work has been done to develop the OpenSHMEM library for PCIe-interconnected HPC systems. This paper introduces a prototype implementation of the OpenSHMEM library through a switchless interconnect network using PCIe NTB to provide a PGAS programming model. In particular, multi-interrupt, multi-thread-based data transfer over the OpenSHMEM shared memory model is applied at the implementation level to reduce the latency and increase the throughput of the switchless ring network system. The implemented OpenSHMEM programming model over the PCIe NTB switchless interconnection network provides a feasible, cost-effective HPC system with a PGAS programming model.

• Journal of IKEEE
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• v.27 no.3
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• pp.355-367
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• 2023

Local Interconnect Network (LIN) is a low-speed in-vehicle network bus, and it is widely used in body applications such as windows, doors, HVAC, and lighting. This review explains protocols and message frames of LIN bus in detail. LIN bus basically transmits ID and payloads in data frame. How to interpret ID and payloads is defined in LIN Description file (LDF). Each LIN bus has unique LDF and its corresponding unique configuration. This review also explains syntax and example of LDF in detail.

• Journal of IKEEE
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• v.22 no.2
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• pp.518-521
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• 2018

IVN (in-vehicle network) connects various electronic modules in the vehicles. It requires real-time, low noise, high reliability, and high flexibility. It includes CAN (controller area network), CAN-FD (CAN flexible data rate), FlexRay, LIN (local interconnect network), SENT (single edge nibble transmission), and PSI5 (peripheral sensor interface 5). In this paper, their operation priciples, target applications, and pros and cons are explained.

• Proceedings of the KSME Conference
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• 2004.11a
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• pp.1740-1745
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• 2004

A simplified resistor network model for electrical and mass transport in anode-supported planar solid oxide fuel cell (SOFC) was constructed in order to investigate the effect of interconnect rib geometry on the cell performance. For accurate potential calculation, activation and concentration over-potentials at the electrode/electrolyte interfaces were fully considered in this calculation. When contact resistance was not considered, the optimum interconnect rib length were calculated to be $0.1{\sim}0.2$ mm for 2 mm half unit cell for given operation conditions and properties. However, with realistic contact resistance, the interconnect rib length should be increased to provide larger contact area and thus to obtain better performance.

• Transactions of the Korean Society of Automotive Engineers
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• v.13 no.6
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• pp.48-55
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• 2005

In this paper, a mathematical model and a simulation method for the response time analysis of Local Interconnect Network(LIN) based network systems are proposed. Network-induced delays in a network based control system can vary widely according to the transmission time of message and the overhead time of transmission. Therefore, in order to design a distributed control system using LIN network, a method to predict and verify the timing behavior of LIN protocol is required at the network design phase. Furthermore, a simulation environment based on a timing model of LIN protocol is beneficial to predict the timing behavior of LIN. The model equation is formulated with six timing parameters deduced from timing properties of LIN specification. Additionally, LIN conformance test equations to verify LIN device driver are derived with timing constraints of the parameters. The proposed model equation and simulation method are validated with a result that is measured at real LIN based network system.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.74-79
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• 2007

In general, the high cost, long time, and complex steps are required in the design and implementation of MPSoC(Multi-Processor System on a Chip), therefore a platform is used to test the functionality and performance of IPs(Intellectual Properties). In this paper, we study a platform architecture to verify IPs based on Interconnect Network among processors, and show that the MPSoC platform gives better performance than a single processor for an application program.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.11
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• pp.83-93
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• 2014

It is a widespread concern that electrical interconnection based network-on-chip (NoC) will ultimately face the limitation in communication bandwidth, transmission latency and power consumption in the near future. With the development of silicon photonics technology, a hybrid optical network-on-chip (HONoC) which embraces both electrical- and optical interconnect, is emerging as a promising solution to overcome these problems. Today's leading edge systems-on-chips (SoCs) comprise heterogeneous many-cores for higher energy efficiency, therefore, extended study beyond regular topology based NoC is required. This paper proposes an energy and latency optimization topology design technique for HONoC taking into account the traffic characteristics of target applications. The proposed technique is implemented with genetic algorithm and simulation results show the reduction by 13.84% in power loss and 28.14% in average latency, respectively.

• Journal of IKEEE
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• v.20 no.3
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• pp.333-336
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• 2016

LIN (local interconnect network) is a standard low-speed serial communication protocol, and it was developed as an efficient sub-bus for automotive electronic modules. In this paper, a LIN controller was implemented in Verilog HDL, based on LIN ver. 2.2A. The implemented LIN controller was verified in FPGA, and it can be supplied as an IP to be integrated into SoC system. Its size is about 2,300 gates when synthesized in 0.18um technology.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 2004.11a
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• pp.43-43
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• 2004