• 전자통신동향분석
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• 제36권3호
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• pp.12-22
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• 2021

Since the technical realization of self-aligned planar complementary metal-oxide-semiconductor field-effect transistors in 1960s, semiconductor manufacturing has aggressively pursued scaling that fruitfully resulted in tremendous advancement in device performances and realization of features sizes smaller than 10 nm. Due to many intrinsic material and technical obstacles, continuing the scaling progress of semiconductor devices has become increasingly arduous. As an effort to circumvent the areal limit, stacking devices in a three-dimensional fashion has been suggested. This approach is commonly called monolithic three-dimensional (M3D) integration. In this work, we examined technical issues that need to be addressed and overcome to fully realize energy efficiency, short latency and cost competency. Full-fledged M3D technologies are expected to contribute to various new fields of artificial intelligence, autonomous gadgets and unknowns, which are to be discovered.

• 한국재료학회:학술대회논문집
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• 한국재료학회 1998년도 IUMRS-ICEM ABSTRACT BOOK
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• pp.52.2-52
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• 1998

• 전자공학회논문지A
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• 제28A권1호
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• pp.46-51
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• 1991

The new signal process circuit using ISFETs as two input devices of a MOS differential amplifier stage for application to a ISFET biosensor was developed and its operational characteristics simulated. For a single chip integration of ISFETs, developed signal process circuit and metal reference electrode, serial studies including process development and chip layout was carried out.

• JSTS:Journal of Semiconductor Technology and Science
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• 제4권3호
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• pp.196-203
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• 2004

A three-dimensional (3D) IC technology platform is presented for high-performance, low-cost heterogeneous integration of silicon ICs. The platform uses dielectric adhesive bonding of fully-processed wafer-to-wafer aligned ICs, followed by a three-step thinning process and copper damascene patterning to form inter-wafer interconnects. Daisy-chain inter-wafer via test structures and compatibility of the process steps with 130 nm CMOS sal devices and circuits indicate the viability of the process flow. Such 3D integration with through-die vias enables high functionality in intelligent wireless terminals, as vertical integration of processor, large memory, image sensors and RF/microwave transceivers can be achieved with silicon-based ICs (Si CMOS and/or SiGe BiCMOS). Two examples of such capability are highlighted: memory-intensive Si CMOS digital processors with large L2 caches and SiGe BiCMOS pipelined A/D converters. A comparison of wafer-level 3D integration 'lith system-on-a-chip (SoC) and system-in-a-package (SiP) implementations is presented.

• 한국실내디자인학회논문집
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• 제27권3호
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• pp.100-107
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• 2018

In order to overcome social exclusion and to integrate social housing, it is necessary to plan a communal space in urban collective housing so that residents can have belonging sense and community consciousness. In this study, it is necessary to consider the linkage between social integration and residential space, and to derive the characteristics of planning the collective housing for social integration. We analyzed the planning characteristics of MVRDV's communal spaces of collective housing and suggested a method of planning communal spaces of urban collective housing for social integration. Urban density is an important tool and background for MVRDV's design methodology. For this reason, MVRDV's collective housing is selected as a case study in this study. As a result of case analysis, openness and connection characteristics should be considered by using various devices such as glass exterior, balcony, and void in planning the communal space in urban collective housing for social integration. However, since it has appeared in many cases, it can be criticized that the application of this is merely a logic. In other words, it is possible to suggest that we should actively introduce less accessible access. This problem should be solved through more case studies.

• ETRI Journal
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• 제32권2호
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• pp.319-326
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• 2010

Photonics offers a solution to data communication between logic devices in computing systems; however, the integration of photonic components into electronic chips is rather limited due to their size incompatibility. Dimensions of photonic components are therefore being forced to be scaled down dramatically to achieve a much higher system performance. To integrate these nano-photonic components, surface plasmon-polaritons and/or energy transfer mechanisms are used to form plasmonic chips. In this paper, the operating principle of plasmonic waveguide devices is reviewed within the mid-infrared spectral region at the 2 ${\mu}m$ to 5 ${\mu}m$ range, including lossless signal propagation by introducing gain. Experimental results demonstrate that these plasmonic devices, of sizes approximately half of the operating free-space wavelengths, require less gain to achieve lossless propagation. Through optimization of device performance by means of methods such as the use of new plasmonic waveguide materials that exhibit a much lower minimal loss value, these plasmonic devices can significantly impact electronic systems used in data communications, signal processing, and sensors industries.

• 진공이야기
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• 제3권1호
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• pp.22-31
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• 2016

Although graphene has been considered as one of the promise materials for future logic devices due to extremely high mobility, its applications in electronics have been limited to a few cases such as a flexible interconnect, and RF devices. Furthermore, most of the studies on graphene devices reported unstable operations, claimed to be due to the poor quality of graphene. Nevertheless, recent studies showed that the electrical performance of graphene field effect transistor could be stabilized even with CVD graphene when well-established integration processes to control the interface of graphene were used. These results indicate that as in the case of silicon devices, a proper control of graphene interface is very important for the stable operation of graphene device as well as other 2D material based devices.

• 전자통신동향분석
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• 제32권6호
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• pp.27-39
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• 2017

A variety of medical devices are utilized to repair or help injured body functions after accidental injury(such as a traffic accident), population aging, or disease. Such medical devices are being actively researched and developed in portable form, skin patchable type, and further, implantable form. In the future, active implantable medical devices for neuro and brain sciences are expected to be developed. Active implantable medical devices that detect brain signals and control neurology for a wider understanding of human cognition and nerve functions, and for an understanding and treatment of various diseases, are being actively pursued for future use. In this paper, the core elements of implantable devices that can be applied to neuro and brain sciences are classified into electrode technologies for bio-signal acquisition and stimulation, analog/digital circuit technologies for signal processing, human body communication technologies, wireless power transmission technologies for continuous device use, and device integration technologies to integrate them. In each chapter, the latest technology development trends for each detailed technology field are reviewed.

• 진공이야기
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• 제1권3호
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• pp.21-27
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• 2014

Advanced process and integration for future semiconductor devices is approaching the physical limit. The new materials with low dimensional structure have recently attracted great attention due to its expandability for the future electronic devices. In order to apply the materials to future semiconductor devices, the control of carrier scattering is critical issue. That is, the carrier scattering with physical quantity in low dimensional structure significantly modulates the device characteristics. We introduce the role of defect in several future semiconductor materials and devices. The analysis of defect in the structure becomes the most important techniques. In particular, surface defect in nano structures totally controls the device characteristics. The changes imply that the metrology field is leading the future industry for semiconductor.

• 한국광학회지
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• 제16권3호
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• pp.196-200
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• 2005

[ $0.75delta\%$ ]의 평판광회로(PLC;Planar Lightwave Circuit)소자의 설계 및 제작기술을 가지고 저손실과 높은 누화율을 가진 파장 다중화 및 역다중화 소자를 개발하였다. C-band AWG(Arrayed Waveguide Grating)에서의 삽입손실은 2.503이하, 누화율은 35dB이상, 균일도는 1dB이하이며 L-band에서는 Vernier 디자인을 적용하여 ITU-T의 파장 정확도가 0.04nm이하가 되도록 제작하였다.