• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.1
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• pp.14-19
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• 2008

Semiconductor testing area challenges many testing issues due to the minimization and ultra high performance of current semiconductors. Among these issues, signal integrity test on interconnections must be solved for highly integrated circuits like SoC. In this paper, we propose an effective pattern application method for signal integrity test on interconnects. Proposed method can be applied by using boundary scan architecture and very efficient test can be preceded with pretty short test time.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.50-56
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• 2000

The integrated circuit interconnection lines are experimented with patterned ground shields (PGS) at microwave frequencies. Measurement results demonstrate that the PGS can significantly reduce the power loss through the interconnect lines over wide frequency ranges as the PGS shields the lossy silicon substrate. The transmission line characteristics of the PGS interconnect lines are analyzed and identified that the PGS reduces the wave length of the interconnect line.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.2
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• pp.65-77
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• 2000

We propose a new formulation by quadratic boolean programming to partition circuits for FPGA based reconfigurable circuit boards, in which the routing topology among IC chips are predetermined. The formulation is to minimize the sum of the wire length by considering the nets passing through IC chips for the interconnections between chips which are not adjacent, in addition to the constraints considered by the previous partition methods. We also describe a heuristic method, which consist of module assignment method to efficiently solve the problem. Experimental results show that our method generates the partitions in which the given constraints are all satisfied for all the benchmark circuits tested. The pin utilization are reduced for the most of the circuits and the total wire length of the routed nets are improved up to 34.7% compared to the previous method.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.10
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• pp.186-194
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• 1996

The SliM (sliding memory plane) array processor has been proposed to alleviate disadvantages of existing mesh-connected SIMD(single instruction stream- multiple data streams) array processors, such as the inter-PE(processing element) communication overhead, the data I/O overhead and complicated interconnections. This paper presents the deisgn and implementation of SliM image processor ASIC (application specific integrated circuit) chip consisting of mesh connected 5 X 5 PE. The PE architecture implemented here is quite different from the originally proposed PE. We have performed the front-end design, such as VHDL (VHSIC hardware description language)modeling, logic synthesis and simulation, and have doen the back-end design procedure. The SliM ASIC chip used the VTI 0.8$\mu$m standard cell library (v8r4.4) has 55,255 gates and twenty-five 128 X 9 bit SRAM modules. The chip has the 326.71 X 313.24mil$^{2}$ die size and is packed using the 144 pin MQFP. The chip operates perfectly at 25 MHz and gives 625 MIPS. For performance evaluation, we developed parallel algorithms and the performance results showed improvement compared with existing image processors.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.5
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• pp.48-55
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• 2010

As the complexity and the clock speed of semiconductor integrated circuits increase, silicon validation becomes important. In this research, we developed new post-silicon repair & revision techniques to reduce cost and time-to-market. Spare cells are fabricated with the original design and are used for repair when necessary. The interconnections are modified by repair layer revision. The repair cost can be reduced by logic partitioning. Experimental results show that these techniques are effective for low-cost and fast turnaround repair.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.8
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• pp.19-26
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• 2004

High performance packages must provide excellent transmission characteristics. In face-up ceramic packages, however, parasitic characteristics of bondwires are not negligible at millimeter-wave frequencies. Consequently, the electrical performance of ceramic packages is degraded. In をis paper, we propose a new millimeter-wave ceramic package feed-through having Embedded Metal Sheets (EMS). The package that contains double-bondwire interconnections is analyzed by the FEM (Finite Element Method) and measured from 20 to 50GHz. As a result, the proposed package having Embedded Metal Sheets (EMS) achieved 0.85dB, 0.4dB insertion loss improvement on the conventional and the double bondwires buried in epoxy ( $\varepsilon_{{\gamma}}$/ = 4) ceramic package respectively to 47GHz. This improved ceramic package will be useful for MMICs modules and small ceramic packages developments.amic packages developments.

• Proceedings of the Korean Vacuum Society Conference
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• 2016.02a
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• pp.93-93
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• 2016

Large scale integrated circuits (LSIs) has been improved by the shrinkage of the circuit dimensions. The smaller chip sizes and increase in circuit density require the miniaturization of the line-width and space between metal interconnections. Therefore, an extreme precise control of the critical dimension and pattern profile is necessary to fabricate next generation nano-electronics devices. The pattern profile control of plasma etching with an accuracy of sub-nanometer must be achieved. To realize the etching process which achieves the problem, understanding of the etching mechanism and precise control of the process based on the real-time monitoring of internal plasma parameters such as etching species density, surface temperature of substrate, etc. are very important. For instance, it is known that the etched profiles of organic low dielectric (low-k) films are sensitive to the substrate temperature and density ratio of H and N atoms in the H2/N2 plasma [1]. In this study, we introduced a feedback control of actual substrate temperature and radical density ratio monitored in real time. And then the dependence of etch rates and profiles of organic films have been evaluated based on the substrate temperatures. In this study, organic low-k films were etched by a dual frequency capacitively coupled plasma employing the mixture of H2/N2 gases. A 100-MHz power was supplied to an upper electrode for plasma generation. The Si substrate was electrostatically chucked to a lower electrode biased by supplying a 2-MHz power. To investigate the effects of H and N radical on the etching profile of organic low-k films, absolute H and N atom densities were measured by vacuum ultraviolet absorption spectroscopy [2]. Moreover, using the optical fiber-type low-coherence interferometer [3], substrate temperature has been measured in real time during etching process. From the measurement results, the temperature raised rapidly just after plasma ignition and was gradually saturated. The temporal change of substrate temperature is a crucial issue to control of surface reactions of reactive species. Therefore, by the intervals of on-off of the plasma discharge, the substrate temperature was maintained within ${\pm}1.5^{\circ}C$ from the set value. As a result, the temperatures were kept within $3^{\circ}C$ during the etching process. Then, we etched organic films with line-and-space pattern using this system. The cross-sections of the organic films etched for 50 s with the substrate temperatures at $20^{\circ}C$ and $100^{\circ}C$ were observed by SEM. From the results, they were different in the sidewall profile. It suggests that the reactions on the sidewalls changed according to the substrate temperature. The precise substrate temperature control method with real-time temperature monitoring and intermittent plasma generation was suggested to contribute on realization of fine pattern etching.