• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.40 no.2
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• pp.157-164
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• 2012

The design strategy of the multi-functional structure is that the electrical components and the circuits are directly put on their supporting structural panel in which the radiation shields and the thermal control functions are integrated. Applying the multi-functional structure reduces the total mass and size of the space system and makes it possible to lower launch cost. In present study the performance of thermal radiation for six types of multi-functional structure are investigated by the numerical method. The effect of the rib configuration on heat transfer for the multi-functional-structure is not important alone but is meaningful considering with the structural stiffness, difficulty of manufacturing and mass increase. In heat spreading point of view, the thickness of the outer conductive layer is important rather than the rib configuration and the trade-off study with the mass and thickness is required for optimum design.

• Proceedings of the Optical Society of Korea Conference
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• 2000.08a
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• pp.28-29
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• 2000

Optical power splitters and/or couplers are important components for optical signal distribution between channels both in wavelength division multiplexing(WDM) systems and photonic integrated circuits(PICs). Since polarization is usually not known after propagation in an optical fiber, passive WDM components have to be polarization insensitivity, Compared to alternatives such as directional couplers or Y-junction splitters, splitters based on multimode interference(MMI) have found a growing interest in recent yens because of their desirable characteristics, such as compact size, low excess loss, wide bandwidth, polarization independence, and relaxed fabrication tolerances$^{(1)}$ . These devices have been fabricated in polymers, silica, or III-V semiconductor materials. A1 $\times$ 4 MMI power splitter on InP materials that were suitable for application in the 1.55-${\mu}{\textrm}{m}$ region$^{(2)}$ . However, the fabrication process of the structure is too complicated and the photolithography tolerance is very tight. Also, a 1 $\times$ 16 InGaAsP/InP MMI power splitter with an excess loss of 2.2dB and a splitting ratio of 1.5dB was demonstrated by using deep etching$^{(3)}$ . The deep etching of the sidewalls through the entire guide layer of the slab waveguide resulted in a number of drawbacks$^{(4)}$ . (omitted)

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.71-71
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• 2012

As the critical dimensions of integrated circuits are scaled down, the line width and spacing between the metal interconnects are made smaller. The dielectric film used as insulation between the metal lines contributes to the resistance-capacitance (RC) time constant that governs the device speed. If the RC time delay, cross talk and lowering the power dissipation are to be reduced, the intermetal dielectric (IMD) films should have a low dielectric constant. The introduction of Cu and low-k dielectrics has incrementally improved the situation as compared to the conventional $Al/SiO_2$ technology by reducing both the resistivity and the capacitance between interconnects. Some of the potential candidate materials to be used as an ILD are organic and inorganic precursors such as hydrogensilsequioxane (HSQ), silsesquioxane (SSQ), methylsilsisequioxane (MSQ) and carbon doped silicon oxide (SiOCH), It has been shown that organic functional groups can dramatically decrease dielectric constant by increasing the free volume of films. Recently, various inorganic precursors have been used to prepare the SiOCH films. The k value of the material depends on the number of $CH_3$ groups built into the structure since they lower both polarity and density of the material by steric hindrance, which the replacement of Si-O bonds with Si-$CH_3$ (methyl group) bonds causes bulk porosity due to the formation of nano-sized voids within the silicon oxide matrix. In this talk, we will be introduce some properties of SiOC(-H) thin films deposited with the dimethyldimethoxysilane (DMDMS: $C_4H_{12}O_2Si$) and oxygen as precursors by using plasma-enhanced chemical vapor deposition with and without ultraviolet (UV) irradiation.

• Ceramist
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• v.21 no.2
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• pp.4-18
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• 2018

Lastly, neuromorphic computing chip has been extensively studied as the technology that directly mimics efficient calculation algorithm of human brain, enabling a next-generation intelligent hardware system with high speed and low power consumption. Three-terminal based synaptic transistor has relatively low integration density compared to the two-terminal type memristor, while its power consumption can be realized as being so low and its spike plasticity from synapse can be reliably implemented. Also, the strong electrical interaction between two or more synaptic spikes offers the advantage of more precise control of synaptic weights. In this review paper, the results of synaptic transistor mimicking synaptic behavior of the brain are classified according to the channel material, in order of silicon, organic semiconductor, oxide semiconductor, 1D CNT(carbon nanotube) and 2D van der Waals atomic layer present. At the same time, key technologies related to dielectrics and electrolytes introduced to express hysteresis and plasticity are discussed. In addition, we compared the essential electrical characteristics (EPSC, IPSC, PPF, STM, LTM, and STDP) required to implement synaptic transistors in common and the power consumption required for unit synapse operation. Generally, synaptic devices should be integrated with other peripheral circuits such as neurons. Demonstration of this neuromorphic system level needs the linearity of synapse resistance change, the symmetry between potentiation and depression, and multi-level resistance states. Finally, in order to be used as a practical neuromorphic applications, the long-term stability and reliability of the synapse device have to be essentially secured through the retention and the endurance cycling test related to the long-term memory characteristics.

• Journal of the Korea Society of Computer and Information
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• v.12 no.3
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• pp.37-50
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• 2007

In this paper, we designed and implementation of the high speed neuron processor for real time object recognition in the making automatic system. and we designed of the PE(Processing Element) used residue number system without carry propagation for the high speed operation. Consisting of MAC(Multiplication and Accumulation) operator using residue number system and sigmoid function operator unit using MAC(Mixed Radix conversion) is designed. The designed circuits are descript by C language and VHDL(Very High Speed Integrated Circuit Hardware Description Language) and synthesized by compass tools and finally, the designed processor is fabricated in $0.8{\mu}m$ CMOS process. we designed of MAC operation unit and sigmoid proceeding unit are proved that it could run time 0.6nsec on the simulation and improved to the speed of the three times and decreased to hardware size about 50%, each order. The designed neuron processor can be implemented of the object recognition in making automatic system with desired real time processing.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.5
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• pp.128-133
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• 2013

In this paper, octagonal inductors for RFIC designs was fabricated with 90nm CMOS Technology to compare its quality factor and the effective inductance as functions of radius and number of turn. The quality factor decreases as the inner radius and the number of metal turned increase. However, the effective inductance increases with the increasing the inner radius and the number of metal turned. Therefore, the inductor structure should be decided according to the relative importance of Q-factor and inductance.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.3
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• pp.632-638
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• 2011

This paper presents on-chip Design-for-Testability (DFT) circuit for radio frequency System-on-Chip (SoC) applications. The proposed circuit measures functional specifications of RF integrated circuits such as input impedance, gain, noise figure, input voltage standing wave ratio (VSWRin) and output signal-to-noise ratio (SNRout) without any expensive external equipment. The RF DFT scheme is based on developed theoretical expressions that produce the actual RF device specifications by output DC voltages from the DFT chip. The proposed DFT showed deviation of less than 2% as compared to expensive external equipment measurement. It is expected that this circuit can save marginally failing chips in the production testing as well as in the RF system; hence, saving tremendous amount of revenue for unnecessary device replacements.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.05c
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• pp.21-23
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• 2004

We report experimental results demonstrating a novel metal defined polymer optical waveguide with a low loss in electro-optic polymers for the first time. The polymer optical waveguides are created using a metal film on the top of upper cladding without any conventional etching process. The fabricated waveguides have an excellent lateral optical mode confinement at both 1.31 ${\square}m$ and 1.55 ${\square}m$ wavelength, resulting in a fiber-to lens optical insertion loss of ~ 7 dB at 1.55 ${\square}m$ and ~4.5 dB at 1.31 ${\square}m$ wavelength in a 3.5cm total length for TM polarizations, respectively. We also present the optical loss dependence of the waveguide as a function of optical wavelengths. These results may be used in the complex design of integrated polymer optical circuits that need simpler and cheaper fabrication process.

• Journal of Semiconductor Engineering
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• v.1 no.1
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• pp.1-12
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• 2020

Handling precise timing in high-speed transceivers has always been a primary design target to achieve better performance. Many different approaches have been tried, and one of those is utilizing the beneficial nature of injection locking. Though the phenomenon was not intended for building integrated circuits at first, its coupling effect between neighboring oscillators has been utilized deliberately. Consequently, the dynamics of the injection-locked oscillator (ILO) have been explored, starting from R. Adler. As many aspects of the ILO were revealed, further studies followed to utilize the technique in practice, suggesting alternatives to the conventional frequency syntheses, which tend to be complicated and expensive. In this review, the historical analysis techniques from R. Adler are studied for better comprehension with proper notation of the variables, resulting in numerical results. In addition, how the timing jitter or phase noise in the ILO is attenuated from noise sources is presented in contrast to the clock generators based on the phase-locked loop (PLL). Although the ILO is very promising with higher cost effectiveness and better noise immunity than other schemes, unless correctly controlled or tuned, the promises above might not be realized. In order to present the favorable conditions, several strategies have been explored in diverse applications like frequency multiplication, data recovery, frequency division, clock distribution, etc. This paper reviews those research results for clock multiplication and data recovery in detail with their advantages and disadvantages they are referring to. Through this review, the readers will hopefully grasp the overall insight of the ILO, as well as its practical issues, in order to incorporate it on silicon successfully.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.12
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• pp.139-145
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• 2008

In this paper, a microstrip surface wave antenna(SWA) with a frequency selective surface structure(FSS) is designed and measured. A microstrip SWA has many advantages such as low profile, low weight, easy fabrication, and compatibility with monolithic microwave integrated circuits(MMIC). In addition, it has demonstrated monopole like beam patterns. The microstrip SWA consists of two parts : a center-fed modified microstrip patch to excite surface wave, and a periodic patches to support the propagation of the surface waves. To obtain wide bandwidth, the ring type parasitic element is inserted and the circular patch is selected for the unit element in FSS structure. Experimental results show that the microstrip SWA has monopole like beam patterns at 5.9GHz. Impedance bandwidth and gain is 12% and 5.6dBi.