• ETRI Journal
• /
• 제30권4호
• /
• pp.546-554
• /
• 2008

Phase-locked loops (PLLs) are among the most important mixed-signal building blocks of modern communication and control circuits, where they are used for frequency and phase synchronization, modulation, and demodulation as well as frequency synthesis. The growing popularity of PLLs has increased the need to test these devices during prototyping and production. The problem of distinguishing and classifying the responses of analog integrated circuits containing catastrophic faults has aroused recent interest. This is because most analog and mixed signal circuits are tested by their functionality, which is both time consuming and expensive. The problem is made more difficult when parametric variations are taken into account. Hence, statistical methods and techniques can be employed to automate fault classification. As a possible solution, we use the back propagation neural network (BPNN) to classify the faults in the designed charge-pump PLL. In order to classify the faults, the BPNN was trained with various training algorithms and their performance for the test structure was analyzed. The proposed method of fault classification gave fault coverage of 99.58%.

• Transactions on Electrical and Electronic Materials
• /
• 제12권1호
• /
• pp.7-10
• /
• 2011

High voltage (HV) integrated circuits are viable alternatives to discrete circuits in a wide variety of applications. A HV device generally used in these circuits is a lateral double diffused metal oxide semiconductor (LDMOS) transistor. Attempts to model LDMOS devices are complicated by the existence of the lightly doped drain and by the extension of the poly-silicon and the gate oxide. Several physically based investigations of the bias-dependent drift resistance of HV devices have been conducted, but a complete physical model has not been reported. We propose a new technique to model HV devices using both the BSIM3 SPICE model and a bias dependent resistor model (sub-circuit macro model).

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2008년도 하계종합학술대회
• /
• pp.499-500
• /
• 2008

In this paper, we design and implement the monolithic power factor correction IC for system power modules using a high voltage(50V) CMOS process. The power factor correction IC is designed for power applications, such as refrigerator, air-conditioner, etc. It includes low voltage logic, 5V regulator, analog control circuit, high-voltage high current output drivers, and several protection circuits. And also, the designed IC has standby detection function which detects the output power of the converter stage and generates system down signal when load device is under the standby condition. The simulation and experimental results show that the designed IC acts properly as power factor correction IC with efficient protective functions.

• Journal of information and communication convergence engineering
• /
• 제6권3호
• /
• pp.270-274
• /
• 2008

This paper proposes an advanced signal processing circuit for a fingerprint sensor based on ridge resistivity. A novel fingerprint integrated sensor using ridge resistivity variation resulting from ridges and valleys on the fingertip is presented. The pixel level simple detection circuit converts from a small and variable sensing current to binary voltage out effectively. The sensor circuit blocks were designed and simulated in a standard CMOS 0.35 ${\mu}m$ process.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제1권3호
• /
• pp.189-192
• /
• 2001

A simple metal-insulator-metal (MIM) capacitor in a standard $0.25{\;}\mu\textrm{m}$ digital CMOS process is described. Using all six interconnect layers, this capacitor exploits both the lateral and vertical electrical fields to increase the capacitance density (capacitance per unit area). Compared to a conventional parallel plate capacitor in the four upper metal layers, this capacitor achieves lower parasitic substrate capacitance, and improves the capacitance density by a factor of 4. Measurements and an extracted model for the capacitor are also presented. Calculations, model and measurements agree very well.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1997년도 하계학술대회 논문집 C
• /
• pp.1311-1313
• /
• 1997

We describe the working principle, the design, and the characteristics of two-chip integrated humidity sensor. The sensing element was manufactured using polyimide. The interface circuits were developed based on a charge redistribution between capacitors. The sensor and signal conditioning chips were packaged together in the same package. The sensor showed excellent linearity over a wide range of relative humidity.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1994년도 하계학술대회 논문집 C
• /
• pp.1388-1390
• /
• 1994

A polyimide-based capacitive humidity sensor has been designed and fabricated using silicon integrated-circuit technology, and its performance measured. The sensor showed excellent linearity, low temperature coefficient, and low hysteresis over a wide range of relative humidity and temperature. The signal conditioning circuits for detecting relative humidity and converting it to voltage have been developed based on a charge redistribution between capacitors using switched -capacitors.

• 한국전기전자재료학회:학술대회논문집
• /
• 한국전기전자재료학회 2008년도 추계학술대회 논문집 Vol.21
• /
• pp.82-82
• /
• 2008

One-dimensional (1D) nanowires have been received much attention due to their potential for applications in various field. Recently some logic applications fabricated on various nanowires, such as ZnO, CdS, Si, are reported. These logic circuits, which consist of two- or three field effect transistors(FETs), are basic components of computation machine such as central process unit (CPU). FETs fabricated on nanowire generally have surrounded shapes of gate structure, which improve the device performance. Highly integrated circuits can also be achieved by fabricating on nano-scaled nanowires. But the numerical and SPICE simulation about the logic circuitry have never been reported and analyses of detailed parameters related to performance, such as channel doping, gate shapes, souce/drain contact and etc., were strongly needed. In our study, NAND and NOT logic circuits were simulated and characterized using 2- and 3-dimensional numerical simulation (SILVACO ATLAS) and built-in spice module(mixed mode).

• 대한전자공학회논문지SD
• /
• 제42권2호
• /
• pp.15-22
• /
• 2005

System-on-Glass 아날로그 회로를 구현하기 위해 요구되는 저항 matching 및 poly-Si TFT 특성을 기존 아날로그 회로를 이용하여 조사하였다. 저항 값, poly-Si TFT의 문턱전압 및 이동도의 matching 조건을 디스플레이 시스템의 해상도에 따라 유도하였다. 또한, 소스 드라이버를 구현하기 위해 요구되는 poly-Si TFT의 유효 이동도를 다양한 패널 크기에 따라서 분석하였다.

• ETRI Journal
• /
• 제32권1호
• /
• pp.151-153
• /
• 2010

A highly efficient linear and compactly integrated series-type Doherty power amplifier (PA) has been developed for wideband code-division multiple access handset applications. To overcome the size limit of a typical Doherty amplifier, all circuit elements, such as matching circuits and impedance transformers, are fully integrated into a single monolithic microwave integrated circuit (MMIC). The implemented PA shows a very low idle current of 25 mA and an excellent power-added efficiency of 25.1% at an output power of 19 dBm by using an extended Doherty concept. Accordingly, its average current consumption was reduced by 51% and 41% in urban and suburban environments, respectively, when compared with a class-AB PA. By adding a simple predistorter to the PA, the PA showed an adjacent channel leakage ratio better than -42 dBc over the whole output power range.