• Title/Summary/Keyword: Integer Linear Programming (ILP)

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Design and Implementation of a Genetic Algorithm for Optimal Placement (최적 배치를 위한 유전자 알고리즘의 설계와 구현)

  • 송호정;이범근
    • Journal of the Korea Society of Computer and Information
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    • v.7 no.3
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    • pp.42-48
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    • 2002
  • Placement is an important step in the physical design of VLSI circuits. It is the problem of placing a set of circuit modules on a chip to optimize the circuit performance. The most popular algorithms for placement include the cluster growth, simulated annealing and integer linear programming. In this paper we propose a genetic algorithm searching solution space for the placement problem, and then compare it with simulated annealing by analyzing the results of each implementation.

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A Scheduling Technique for Pipelined Datapath Synthesis (파이프라인형 데이타패스 합성을 위한 스케쥴링 기법)

  • 이근만;임인칠
    • Journal of the Korean Institute of Telematics and Electronics A
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    • v.29A no.4
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    • pp.74-82
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    • 1992
  • This paper deals with the scheduling problems, which are the most important subtask in High-level Synthesis. ILP(integer linear programming) formulations are used as a scheduling problem approach.For practical application to digital system design, we have concentrated our attentions on pipelined datapath scheduling. For experiment results, we choose the 5-th order digital wave filter as a benchmark and do the schedule. Finally, we can obtain better and near-optimal scheduling results.

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Optimal Task Scheduling for Minimizing Energy Consumption in I/O Devices (입/출력 장치의 소비전력 최적화를 위한 타스크 스케줄링)

  • 정도한;김태환
    • Proceedings of the Korean Information Science Society Conference
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    • 2004.10a
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    • pp.574-576
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    • 2004
  • 임베디드 시스템에서 입출력에서 소모되는 전력양은 상당한 수준이다. 입출력 장치에서의 수행되는 타스크의 순서를 정하여 전체적으로 입출력 장지에서의 휴식 시간을 최대한 많이 허락하는 기법이 필요하다. 기존의 연구는 입출력 장치 소비 전력 최소화를 위한 타스크 스케줄링 문제를 단순한 지협적인 휴리스틱에 기반하여 풀었다. 본 연구는 기존의 연구에서의 방법과는 달리 최적의 해를 내는 해법을 제시한다. 구체적으로 시간 제약 조건을 가진 저전력을 위한 타스크 스케줄링 문제를 ILP (integer linear programming) 기법을 적용하는 방법을 제시한다. 본 연구는 또한, 실험을 통해 주어진 시간 안에 최적의 해를 구하는 문제의 크기를 판단하는 기준을 제시할 수 있다는 의의를 가진다.

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Dynamic Code Placement Techniques for Scratch-Pad Memory (Scratch-Pad 메모리를 위한 동적 코드 배치 기법)

  • Kim Chihun;Jang Choonki;Lee Jaejin;Min Sang Lyul
    • Proceedings of the Korean Information Science Society Conference
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    • 2005.07a
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    • pp.784-786
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    • 2005
  • SPM (Scratch-Pad Memory)을 위한 코드 배치 기법과 demand paging기법을 Post pass optimizer를 사용하여 구현한다. 코드 배치 문제는 ILP (Integer Linear Programming) 문제로 변환하여 해결한다. 최적 화기는 ILP 해답의 질을 높이기 위해 응용 프로그램의 프로파일 정보를 사용하고, 코드로부터 natural loop을 추출한다. 또한 SPM을 사용하여 demand paging을 할수 있도록 추가 코드를 삽입한다. 이 기법을 사용해 6개의 내장형 응용 프로그램을 실험하였고, 프로그램 크기의 $20\%$에 해당하는 SPM에 대해 전력 소모는 $75.9\%$로 감소하였고 성능은 $54.5\%$ 증가하였다.

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Closed Walk Ferry Route Design for Wireless Sensor Networks

  • Dou, Qiang;Wang, Yong;Peng, Wei;Gong, Zhenghu
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.7 no.10
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    • pp.2357-2375
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    • 2013
  • Message ferry is a controllable mobile node with large capacity and rechargeable energy to collect information from the sensors to the sink in wireless sensor networks. In the existing works, route of the message ferry is often designed from the solutions of the Traveling Salesman Problem (TSP) and its variants. In such solutions, the ferry route is often a simple cycle, which starts from the sink, access all the sensors exactly once and moves back to the sink. In this paper, we consider a different case, where the ferry route is a closed walk that contains more than one simple cycle. This problem is defined as the Closed Walk Ferry Route Design (CWFRD) problem in this paper, which is an optimization problem aiming to minimize the average weighted delay. The CWFRD problem is proved to be NP-hard, and the Integer Linear Programming (ILP) formulation is given. Furthermore, a heuristic scheme, namely the Initialization-Split-Optimization (ISO) scheme is proposed to construct closed walk routes for the ferry. The experimental results show that the ISO algorithm proposed in this paper can effectively reduce the average weighted delay compared to the existing simple cycle based scheme.

A Dynamic Placement Mechanism of Service Function Chaining Based on Software-defined Networking

  • Liu, Yicen;Lu, Yu;Chen, Xingkai;Li, Xi;Qiao, Wenxin;Chen, Liyun
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.12 no.10
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    • pp.4640-4661
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    • 2018
  • To cope with the explosive growth of Internet services, Service Function Chaining (SFC) based on Software-defined Networking (SDN) is an emerging and promising technology that has been suggested to meet this challenge. Determining the placement of Virtual Network Functions (VNFs) and routing paths that optimize the network utilization and resource consumption is a challenging problem, particularly without violating service level agreements (SLAs). This problem is called the optimal SFC placement problem and an Integer Linear Programming (ILP) formulation is provided. A greedy heuristic solution is also provided based on an improved two-step mapping algorithm. The obtained experimental results show that the proposed algorithm can automatically place VNFs at the optimal locations and find the optimal routing paths for each online request. This algorithm can increase the average request acceptance rate by about 17.6% and provide more than 20-fold reduction of the computational complexity compared to the Greedy algorithm. The feasibility of this approach is demonstrated via NetFPGA-10G prototype implementation.

Bus and Registor Optimization in Datapath Synthesis (데이터패스 합성에서의 버스와 레지스터의 최적화 기법)

  • Sin, Gwan-Ho;Lee, Geun-Man
    • The Transactions of the Korea Information Processing Society
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    • v.6 no.8
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    • pp.2196-2203
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    • 1999
  • This paper describes the bus scheduling problem and register optimization method in datapath synthesis. Scheduling is process of operation allocation to control steps in order to minimize the cost function under the given circumstances. For that purpose, we propose some formulations to minimize the cost function for bus assignment to get an optimal and minimal cost function in hardware allocations. Especially, bus and register minimization technique are fully considered which are the essential topics in hardware allocation. Register scheduling is done after the operation and bus scheduling. Experiments are done with the DFG model of fifth-order digital ware filter to show its effectiveness. Structural integer programming formulations are used to solve the scheduling problems in order to get the optimal scheduling results in the integer linear programming environment.

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An Efficient Service Function Chains Orchestration Algorithm for Mobile Edge Computing

  • Wang, Xiulei;Xu, Bo;Jin, Fenglin
    • KSII Transactions on Internet and Information Systems (TIIS)
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    • v.15 no.12
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    • pp.4364-4384
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    • 2021
  • The dynamic network state and the mobility of the terminals make the service function chain (SFC) orchestration mechanisms based on static and deterministic assumptions hard to be applied in SDN/NFV mobile edge computing networks. Designing dynamic and online SFC orchestration mechanism can greatly improve the execution efficiency of compute-intensive and resource-hungry applications in mobile edge computing networks. In order to increase the overall profit of service provider and reduce the resource cost, the system running time is divided into a sequence of time slots and a dynamic orchestration scheme based on an improved column generation algorithm is proposed in each slot. Firstly, the SFC dynamic orchestration problem is formulated as an integer linear programming (ILP) model based on layered graph. Then, in order to reduce the computation costs, a column generation model is used to simplify the ILP model. Finally, a two-stage heuristic algorithm based on greedy strategy is proposed. Four metrics are defined and the performance of the proposed algorithm is evaluated based on simulation. The results show that our proposal significantly provides more than 30% reduction of run time and about 12% improvement in service deployment success ratio compared to the Viterbi algorithm based mechanism.

BILI-Hardware/Software Partition Heuristic (BILI-하드웨어/소프트웨어 분할 휴리스틱)

  • Oh Hyun-Ok;Ha, Soon-Hoi
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.37 no.9
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    • pp.66-77
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    • 2000
  • This paper presents a fast partitioning heuristic for hardware/software codesign called Best Imaginary Level-Iterative(BILI) partitioning which iteratively applies BIL heterogeneous multiprocessor scheduling heuristic to minimize the cost within the given time constraint. The proposed algorithm solves the partitioning problem with the implementation bin selection problem as well as architectures with multiple software modules. It costs about 15% less than the GCLP and at most about 5% more than the optimal solution obtained by the Integer Linear Programming(ILP) algorithm.

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Energy-efficient charging of sensors for UAV-aided wireless sensor network

  • Rahman, Shakila;Akter, Shathee;Yoon, Seokhoon
    • International Journal of Internet, Broadcasting and Communication
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    • v.14 no.4
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    • pp.80-87
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    • 2022
  • Lack of sufficient battery capacity is one of the most important challenges impeding the development of wireless sensor networks (WSNs). Recent innovations in the areas of wireless energy transfer and rechargeable batteries have made it possible to advance WSNs. Therefore, in this article, we propose an energy-efficient charging of sensors in a WSN scenario. First, we have formulated the problem as an integer linear programming (ILP) problem. Then a utility function-based greedy algorithm named UGreedy/UF1 is proposed for solving the problem. Finally, the performance of UGreedy/UF1 is analyzed along with other baseline algorithms: UGreedy/UF2, 2-opt TSP, and Greedy TSP. The simulation results show that UGreedy/UF1 performs better than others both in terms of the deadline missing ratio of sensors and the total energy consumption of UAVs.