• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.117-120
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• 2001

This paper presents a HW/SW co-design environments and its validation for development of virtual component on the 32-bit RISC core which is used in the design of Information-Appliance-On-a-Chip. For the experimental environment, we developed the cycle-accurate instruction set simulator based on SE3208 RISC core of ADChips. To verify the function of RISC core at the cycle level, we implemented the verification environment by grafting this simulator on the Seamless CVE which is a commercial co-verification environment.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2534-2536
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• 2002

This paper presents the design of high speed bit and word processor for sequence logic control using a FPGA. This FPGA is able to execute sequence instruction during program fetch cycle, because the program memory was separated from the data memory for high speed execution at 40MHz clock. Also this processor has 274 instructions set with a 32bit fixed width, so instruction decoding time and data memory interface time was reduced. This FPGA was synthesized by V600EHQ240 and Foundation tool of Xilinx company. The final simulation was successfully performed under Foundation tool simulation environment. And the FPGA programmed by VHDL for a 240 pin HQFP package. Finally the benchmark was performed to prove that the designed for bit and word processor has better performance than Q4A of Mitsubishi for the sequence logic control.

• Journal of IKEEE
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• v.12 no.4
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• pp.246-254
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• 2008

This paper represents a design of a 4 way SIMD processor with multi-thread and dual phase instruction pipeline. 8 threads can be performing in round-robin order, so any hazards can’t occur. The dual phase pipeline makes a pipeline operate as two pipelines, and it can fetch maximum 4 unit instructions at once. This variable length instruction set divide into first phase and second phase instructions, and with this function, complex branch and addressing can be executed at one clock cycle. This processor reduces the code size to quarter, pull out the doubled performance improvement than normal SIMD architecture.

• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.232-235
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• 1999

In this paper, we present a coprocessor that can operate with ARM microprocessors. The coprocessor supports IEEE 754 standard single- and double-precision binary floating point arithmetic operations. The design objective is to achieve minimum-area, low-power and acceleration of processing power of ARM microprocessors. The instruction set is compatible with ARM7500FE. The coprocessor is written in verilog HDL and synthesized by the SYNOPSYS Design Compiler. The gate count is 38,115 and critical path delay is 9.52ns.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.2
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• pp.820-822
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• 2005

We have designed a 32-bit microprocessor with fixed point digital signal processing functionality. This processor, combines both general-purpose microprocessor and digital signal processor functionality using the reduced instruction set computer design principles. It has functional units for arithmetic operation, digital signal processing and memory access. They operate in parallel in order to remove stall cycles after DSP or load/store instructions, which usually need one or more issue latency cycles in addition to the first issue cycle. High performance was achieved with these parallel functional units while adopting a sophisticated five-stage pipeline stucture.

• The Journal of Korean Society for School & Community Health Education
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• v.10 no.2
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• pp.1-13
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• 2009

Objectives: This study is a quasi-experimental research with nonequivalent control group pretest-posttest design study to compare and verify the educational effects between CPR Song.Video Self-Instruction and CPR VSI. Method: We selected total 58 subjects who were freshmen at the Dept of Emergency Medical technology, G College in G Metropolitan City and 28 of them were experimental group which had no experience to have CPR instruction and consented to take part in this research and 30 students were control group. Data were collected from Apr. 27 to 29, 2009. Data were analyzed with SPSS/PC+(version 14.0). and all significance level was set as p<0.05. Results: 1. In the knowledge of CPR, the knowledge level before CPR instruction was 2.17 out of 10 in experimental group and 1.86 in control group. After CPR instruction, experimental group got 9.07 and it meant the increase of 6.89 and control group showed increase to 7.16(p=0.000). 2. Self-efficacy of CPR showed 2.61 out of 10 in both experimental and control groups, and after CPR instruction, experimental group showed increase of 3.93 as 6.55 and control group showed increase of 3.91 as 6.52(p=0.000). 3. Accuracy of CPR performance was 0.32 out of 10 in experimental group and 0.40 in control group. After CPR instruction, experimental group got 9.25 and showed increase of 8.92 and control group got 9.20 and showed increase of 8.80(p=0.000). 4. Study satisfaction was 4.22 out of 5 in experimental group and 3.04 in control group, and experimental group was higher than control group. there was no statistically significant difference. Conclusions: This study found that CPR Song；Video Self-Instruction achieved better results than CPR VSI. With these results, it is considered that CPR instruction for college students through mass communication or video will be very helpful.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.32B no.1
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• pp.21-29
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• 1995

In this paper, a independent and structured microassembler was designed for easily changing the system design, and for designing various microarchitecture. When the designer's hardware and microprogramming process were made concurrently, it is needed to easily change or improve the instruction set and executable code format. But this type of developed environment requires a high const and a large software system. A proposed microassembler was designed so the designer directly defines the microinstruction set and format to be executed. And we implemented a module from each part of the software, so it is now possible to use practically and upgrade the function of each part, First, the symbol was separated from the assembler. And then microinstruction was copied into it. The microinstruction format was designed using the defined language that was designed for free microinstruction. This was implemented in an IBM-PC by using the C-language, FLEX,and BISON.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.333-340
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• 2017

In this paper, we describe HW/SW co-optimizations for reconfigurable application specific instruction-set processors (ASIPs). Based on our previous very long instruction word (VLIW) ASIP, the proposed framework realizes various forward error-correction (FEC) algorithms for wireless communication systems. In order to enhance the energy efficiency, we newly introduce several design methodologies including high-radix algorithms, task-level out-of-order executions, and intensive resource allocations with loop-level rescheduling. The case study on the radix-4 turbo decoding shows that the proposed techniques improve the energy efficiency by 3.7 times compared to the previous architecture.

• IEIE Transactions on Smart Processing and Computing
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• v.4 no.5
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• pp.366-370
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• 2015

This paper proposes a method for improving a branch predictor for the extendable instruction set computer (EISC) processor. The original EISC branch predictor has several shortcomings: a small branch target buffer, absence of a global history, a one-bit local branch history, and unsupported prediction of branches following LERI, which is a special instruction to extend an immediate value. We adopt a G-share branch predictor and eliminate the existing shortcomings. We verified the new branch predictor on a field-programmable gate array with the Dhrystone benchmark. The newly proposed EISC branch predictor also accomplishes higher branch prediction accuracy than a conventional branch predictor.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.1
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• pp.1-8
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• 2022

RISC-V is an open-source instruction set architecture which has a simple base structure and can be extensible depending on the purpose. In this paper, we designed a small and low-power 32-bit RISC-V processor to establish the base for research on RISC-V embedded systems. We designed a 2-stage pipelined processor which supports RISC-V base integer instruction set except for FENCE and EBREAK instructions. The processor also supports privileged ISA for trap handling. It used 1895 LUTs and 1195 flip-flops, and consumed 0.001W on Xilinx Zynq-7000 FPGA when synthesized using Vivado Design Suite. GPIO, UART, and timer peripherals are additionally used to compose the system. We verified the operation of the processor on FPGA with FreeRTOS at 16MHz. We used Dhrystone and Coremark benchmarks to measure the performance of the processor. This study aims to provide a low-power, high-efficiency microprocessor for future extension.