• Journal of the Korean Society for information Management
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• v.23 no.1 s.59
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• pp.5-39
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• 2006

Design discipline requires more specialized and sophisticated information literacy competencies necessary to effectively find and apply the information that students need for their teaming and the future independent designer than are outlined in general information literacy competencies. Therefore, The goals of this study is to identify specific information literacy competencies within the Design Discipline. This research analyzed design-specific core information literacy competencies through the literature analysis on the design goals & curriculum of four domestic universities and the NASAD standards & guidelines and verified those by Delphi Survey. The result showed that design discipline requires commonly 26 specific core competencies in seven broad categories and the these competencies are related to the time for information literacy Instruction. Also, The result analyzed that such majors in design as product design, visual design, need additionally more specialized and detailed competencies with specific focus and that design discipline requires commonly the information literacy competencies about general studies & fundamental ability.

• Journal of Korea Multimedia Society
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• v.14 no.3
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• pp.462-470
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• 2011

Retargetability is typically achieved by providing target machine information, ADL, as input. The ADL are used to specify processor and memory architectures and generate software toolkit including compiler, simulator, etc. Simulator are critical components of the exploration and software design toolkit for the system designer. They can be used to perform diverse tasks such as verifying the functionality and/or timing behavior of the system, and generating quantitative measurements(e.g., power energy consumption) which can be used to aid the design process. In this paper, we generate the energy consumption estimation simulator through ADL. For this goal, firstly, we describes the energy consumption estimation and monitoring informations on the ADL based on EXPRESSION. Secondly, we generate the energy estimation and monitoring simulation library and then constructs the simulator, RenergySim. Lastly, we represent the energy estimations results for MIPS R4000 ADL description. From this subjects, we contribute to the efficient architecture developments and prompt SDK generation through programmable experiments in the field of mobile software development.

• Human Ecology Research
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• v.55 no.5
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• pp.555-566
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• 2017

This study analyzes the practical tasks and required competency for technical designers to provide basic data on the training of domestic technical designers. The survey was applied to 21 technical designers of big vendors as well as investigated tasks, task flow, important tasks, time-consuming tasks, and required competencies. The results of the study are as follows. First, the technical designers were in charge of several brands of buyers and distributors of fashion companies, or several lines of the same brand. The main production items were cut and sewn knits. Second, the flow of task and tasks were in the order of buyer comments analysis, sloper decision to matching style, sewing specification, productive sewing method research, size specification suggestion, pattern correction comments, construction decision to matching style & fabric, sample evaluations, fit approval, business e-mail writing, specification & grading confirmation, and communication with buyer. Third, five tasks (analysis of buyer comments analysis, communication with buyer, pattern correction comments, productive sewing methods research, sample evaluation) were important and time-consuming tasks. Fourth, reeducation was required in order of sewing, pattern, English, fabric, and fitting. Fifth, competencies to be a technical designers were fitting, pattern correction, size specification & grading, construction & sewing specification, sewing terms & techniques, and communication skills. In conclusion, technical designer training should focus on technology-based instruction, such as sample evaluation, fitting, pattern correction, and productive sewing methods research of cut and sewn knits.

• Journal of Korea Multimedia Society
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• v.10 no.12
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• pp.1679-1686
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• 2007

In this paper, we introduce the sharable and reusable learning objects which are suitable for XML Web services in e-learning systems. These objects are extracted from the principles of pedagogical paradigms for reusable learning units. We call them LIO (Learning Item Object) objects. Existing models, such as Web-hosted and ASP-oriented service model, are difficult to cooperate and integrate among the different kinds of e-learning systems. So we developed the LIO objects that are suitable for XML Web services. The reusable units that are extracted from pedagogical paradigms are tutorial item, resource, case example, simulation, problems, test, discovery and discussion. And these units correspond to the LIO objects in our learning object model. As a result, the proposed model is that learner and instruction designer should increase the power of understanding about learning contents that are based on pedagogical paradigms. By using XML Web services, this guarantees the integration and interoperation of the different kinds of e-learning systems in distributed environments and so educational organizations can expect the cost reduction in constructing e-learning systems.

• Journal of the Korea Institute of Building Construction
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• v.8 no.5
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• pp.75-83
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• 2008

Larger and more sophisticated building construction requires more input resources such as worker, materials and devices. Growing resource volume brings risks at a construction site. The industry makes an effort to protect probable incidents at the site by organizing a safety management team. conducting a safety instruction and etc, but losses especially in the construction are higher than other industries. Major reason is that the safety management program is conducted only at the step of construction work and a root cause is not eliminated. Conventionally a concerned party shifts the blame to other parties such as constructor and site workers who are direct participants in the construction site. However, the whole causes of incidents go to the all subject of the construction not only the constructor but the client, designer and others related in the construction, and especially the clients are heavily involved in general concerns of the project. Therefore, this study is defined the role of the clients in nations and domestic condition of construction safety management is investigated. And it is analyzed surveys to prevent incidents at construction sites, and suggested the role of the clients which is classified pre and post construction, and in the middle of construction, and also categorized planning and design & construction schedule especially for the pre-construction level.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.95-101
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• 2009

Random numbers are used in many sorts of applications. Some applications, like simple software simulation tests, communication protocol verifications, cryptography verification and so forth, need various levels of randomness with various process speeds. In this paper, we propose a fast pseudorandom generator module for embedded systems. The generator module is implemented in hardware which can run in two modes, one of which can generate random numbers with higher randomness but which requires six cycles, the other providing its result within one cycle but with less randomness. An ASIP (Application Specific Instruction set Processor) was designed to implement the proposed pseudorandom generator instruction sets. We designed a processor based on the MIPS architecture,, by using LISA, and have run statistical tests passing the sequence of the Diehard test suite. The HDL models of the processor were generated using CoWare's Processor Designer and synthesized into the Dong-bu 0.18um CMOS cell library using the Synopsys Design Compiler. With the proposed pseudorandom generator module, random number generation performance was 239% faster than software model, but the area increased only 2.0% of the proposed ASIP.

• The Journal of the Korea Contents Association
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• v.10 no.12
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• pp.129-136
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• 2010

Smartphone used to be an it item for only business people and early adaptors. However, the public interest towards Smartphone has been rapidly increased and now is spreading to the everyday life in general people. Variety of applications are introduced and registered in a day, but there are not enough apps with simple and useable interface. This is because that the applications are developed only in a view from developer and designer to match the splendor design and technical skills of apps not concerning the users. Therefore this study will analyze the value in use and design trend of registered apps in apps store to recognize the importance in use and also to discuss about a plan to apply this into the apps more effectively. In order to improve the mobile app usability, this study suggest that using intuitional icon, designing easy to use app navigation. This will lead to produce clear instruction for app developers and designers with more reliable effects in the future of Smartphone world.

• Proceedings of the Korean Institute of Intelligent Systems Conference
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• 1993.06a
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• pp.975-976
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• 1993

This talk presents the overview of the author's research and development activities on fuzzy inference hardware. We involved it with two distinct approaches. The first approach is to use application specific integrated circuits (ASIC) technology. The fuzzy inference method is directly implemented in silicon. The second approach, which is in its preliminary stage, is to use more conventional microprocessor architecture. Here, we use a quantitative technique used by designer of reduced instruction set computer (RISC) to modify an architecture of a microprocessor. In the ASIC approach, we implemented the most widely used fuzzy inference mechanism directly on silicon. The mechanism is beaded on a max-min compositional rule of inference, and Mandami's method of fuzzy implication. The two VLSI fuzzy inference chips are designed, fabricated, and fully tested. Both used a full-custom CMOS technology. The second and more claborate chip was designed at the University of North Carolina(U C) in cooperation with MCNC. Both VLSI chips had muliple datapaths for rule digital fuzzy inference chips had multiple datapaths for rule evaluation, and they executed multiple fuzzy if-then rules in parallel. The AT & T chip is the first digital fuzzy inference chip in the world. It ran with a 20 MHz clock cycle and achieved an approximately 80.000 Fuzzy Logical inferences Per Second (FLIPS). It stored and executed 16 fuzzy if-then rules. Since it was designed as a proof of concept prototype chip, it had minimal amount of peripheral logic for system integration. UNC/MCNC chip consists of 688,131 transistors of which 476,160 are used for RAM memory. It ran with a 10 MHz clock cycle. The chip has a 3-staged pipeline and initiates a computation of new inference every 64 cycle. This chip achieved an approximately 160,000 FLIPS. The new architecture have the following important improvements from the AT & T chip: Programmable rule set memory (RAM). On-chip fuzzification operation by a table lookup method. On-chip defuzzification operation by a centroid method. Reconfigurable architecture for processing two rule formats. RAM/datapath redundancy for higher yield It can store and execute 51 if-then rule of the following format: IF A and B and C and D Then Do E, and Then Do F. With this format, the chip takes four inputs and produces two outputs. By software reconfiguration, it can store and execute 102 if-then rules of the following simpler format using the same datapath: IF A and B Then Do E. With this format the chip takes two inputs and produces one outputs. We have built two VME-bus board systems based on this chip for Oak Ridge National Laboratory (ORNL). The board is now installed in a robot at ORNL. Researchers uses this board for experiment in autonomous robot navigation. The Fuzzy Logic system board places the Fuzzy chip into a VMEbus environment. High level C language functions hide the operational details of the board from the applications programme . The programmer treats rule memories and fuzzification function memories as local structures passed as parameters to the C functions. ASIC fuzzy inference hardware is extremely fast, but they are limited in generality. Many aspects of the design are limited or fixed. We have proposed to designing a are limited or fixed. We have proposed to designing a fuzzy information processor as an application specific processor using a quantitative approach. The quantitative approach was developed by RISC designers. In effect, we are interested in evaluating the effectiveness of a specialized RISC processor for fuzzy information processing. As the first step, we measured the possible speed-up of a fuzzy inference program based on if-then rules by an introduction of specialized instructions, i.e., min and max instructions. The minimum and maximum operations are heavily used in fuzzy logic applications as fuzzy intersection and union. We performed measurements using a MIPS R3000 as a base micropro essor. The initial result is encouraging. We can achieve as high as a 2.5 increase in inference speed if the R3000 had min and max instructions. Also, they are useful for speeding up other fuzzy operations such as bounded product and bounded sum. The embedded processor's main task is to control some device or process. It usually runs a single or a embedded processer to create an embedded processor for fuzzy control is very effective. Table I shows the measured speed of the inference by a MIPS R3000 microprocessor, a fictitious MIPS R3000 microprocessor with min and max instructions, and a UNC/MCNC ASIC fuzzy inference chip. The software that used on microprocessors is a simulator of the ASIC chip. The first row is the computation time in seconds of 6000 inferences using 51 rules where each fuzzy set is represented by an array of 64 elements. The second row is the time required to perform a single inference. The last row is the fuzzy logical inferences per second (FLIPS) measured for ach device. There is a large gap in run time between the ASIC and software approaches even if we resort to a specialized fuzzy microprocessor. As for design time and cost, these two approaches represent two extremes. An ASIC approach is extremely expensive. It is, therefore, an important research topic to design a specialized computing architecture for fuzzy applications that falls between these two extremes both in run time and design time/cost. TABLEI INFERENCE TIME BY 51 RULES {{{{Time }}{{MIPS R3000 }}{{ASIC }}{{Regular }}{{With min/mix }}{{6000 inference 1 inference FLIPS }}{{125s 20.8ms 48 }}{{49s 8.2ms 122 }}{{0.0038s 6.4㎲ 156,250 }} }}