• Journal of Electrical Engineering and Technology
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• v.13 no.3
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• pp.1251-1264
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• 2018

The systematic and effective design method of a Class-D current-source resonant inverter for use in an induction cooker with zero-ripple line current is presented. The design procedure is based on the principle of the Class-D current-source resonant inverter with a simplified load network model that is a parallel equivalent circuit. An induction load characterization is obtained from a large-signal excitation test-bench based on parallel load network, which is the key to an accurate design for the induction cooker system. Accordingly, the proposed scheme provides a systematic, precise, and feasible solution than the existing design method based on series-parallel load network under low-signal excitation. Moreover, a zero-ripple condition of utility-line input current is naturally preserved without any extra circuit or control. Meanwhile, a differential-mode input electromagnetic interference (EMI) filter can be eliminated, high power quality in utility-line can be obtained, and a standard-recovery diode of bridge-rectifier can be employed. The step-by-step design procedure explained with design example. The devices stress and power loss analysis of induction cooker with a parallel load network under large-signal excitation are described. A 2,500-W laboratory prototype was developed for $220-V_{rms}/50-Hz$ utility-line to verify the theoretical analysis. An efficiency of the prototype is 96% at full load.

• Journal of IKEEE
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• v.22 no.4
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• pp.896-900
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• 2018

Traditionally, Linear Shift Feedback Register (LFSR) has been widely employed to implement Cyclic Redundant Check (CRC) codes for a serial input. Since many applications including network and storage systems demand as high throughput as ever, various efforts have been made to implement CRC hardware to support parallel inputs. Among various parallel schemes, the look-ahead scheme is one of the most widely used schemes due to its short critical path. However, it is very cumbersome to design HDL codes for parallel CRC codes since the look-ahead scheme is inevitable to consider how register and input values move in the next cycles. Thus, this paper proposes a novel CRC hardware generator, which automatically produces HDL codes given a CRC polynomial and parallel factor. The experimental results verify the applicability to use the proposed generator by analyzing the synthesis results from the generated HDL code.

• The Transactions of the Korea Information Processing Society
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• v.2 no.6
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• pp.969-973
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• 1995

In this paper, a new parallel Multiplier array is proposed to reduce the multiplication time by modifying CAS(carry select adder) cell structure used in the conventional parallel multiplier array. It is named MCSA(modified CSA) that assignes the addend and augend to the inputs of CSA faster than Ci(carry input). Also the designed DCSA (doubled inverted input CSA) is appended after the last product term for the carry propagation adder. The proposed scheme is designed with MCSA and DCSA, and simulated. It is verified that the circuit size is increased about 13% compared with the conventional multiplier array with CSA cell but the operation time is reduced about 52%.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.8
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• pp.139-147
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• 2014

We address the problem of corrective control for two asynchronous sequential machines in parallel connection. Each asynchronous machine receives the same external input and shows independent state transition characteristics. We propose a novel control scheme in which only one corrective controller is employed so as to make the closed-loop system of each machine match the behavior of the corresponding reference model. Compared with the former method utilizing two corrective controllers, our scheme can reduce the controller size and computational load in controller design. We present the existence condition and design procedure for a state-feedback corrective controller under the assumption that the controlled machines are of input/state type. The design procedure for the proposed controller is described in an illustrative example.

• Journal of the Korean Institute of Intelligent Systems
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• v.10 no.2
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• pp.113-121
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• 2000

This paper presents a parallel-structure fuzzy system(PSFS) for prediction of time series data. The PSFS consists of a multiple number of fuzzy systems connected in parallel. Each component fuzzy system in the PSFS predicts the same future data independently based on its past time series data with different embedding dimension and time delay. The component fuzzy systems are characterized by multiple-input singleoutput( MIS0) Sugeno-type fuzzy rules modeled by clustering input-output product space data. The optimal embedding dimension for each component fuzzy system is chosen to have superior prediction performance for a given value of time delay. The PSFS determines the final prediction result by averaging the outputs of all the component fuzzy systems excluding the predicted data with the minimum and the maximum values in order to reduce error accumulation effect.

• Proceedings of the KIEE Conference
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• 1999.07e
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• pp.2201-2203
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• 1999

In this study, we have designed and manufactured not a present elliptic cavity but a circular cavity and we have experimented the operational characteristics. As a result, we obtained the maximum efficiency of 2.1 %. It didn't have any difference compared with elliptic cavity. A circular cavity is much more compact, so far easier to be manufactured than a elliptic cavity. And it can be made at a low cost. At the input energy, parameter $\alpha$, input voltage, and pulse width were in the same condition, we have decided to the optimization of the mesh number of a parallel-mesh circuit which was connected with main power supply.

• Journal of Power Electronics
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• v.12 no.4
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• pp.528-537
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• 2012

This paper presents an interleaved resonant converter with a parallel-series transformer connection in order to achieve ripple current reduction at the output capacitor, zero voltage turn-on for the active switches, zero current turn-off for the rectifier diodes, less voltage stress on the rectifier diodes, and less current stress on the transformer primary windings. The primary windings of the two transformers are connected in parallel in order to share the input current and to reduce the root-mean-square (rms) current on the primary windings. The secondary windings of the two transformers are connected in series in order to ensure that the transformer primary currents are balanced. A full-wave diode rectifier is used at the output side to clamp the voltage stress of the rectifier diode at the output voltage. Two circuit modules are operated with the interleaved PWM scheme so that the input and output ripple currents are reduced. Based on the resonant behavior, all of the active switches are turned on under zero voltage switching (ZVS), and the rectifier diodes are turned off under zero current switching (ZCS) if the operating switching frequency is less than the series resonant frequency. Finally, experiments with a 1kW prototype are described to verify the effectiveness of the proposed converter.

• Journal of information and communication convergence engineering
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• v.14 no.4
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• pp.252-257
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• 2016

An edge-located electromagnetic bandgap (EL-EBG) structure using a defected ground structure (DGS) is proposed to suppress resonant modes induced by edge excitation in a two-dimensional planar parallel plate waveguide (PPW). The proposed EL-DGS-EBG PPW significantly mitigates multiple transverse-magnetic (TM) modes in a wideband frequency range corresponding to an EBG stopband. To verify the wideband suppression, test vehicles of a conventional PPW, a PPW with a mushroom-type EBG structure, and an EL-DGS-EBG PPW are fabricated using a commercial process involving printed circuit boards (PCBs). Measurements of the input impedances show that multiple resonant modes of the previous PPWs are significantly excited through an input port located at a PPW edge. In contrast, resonant modes in the EL-DGS-EBG PPW are substantially suppressed over the frequency range of 0.5 GHz to 2 GHz. In addition, we have experimentally demonstrated that the EL-DGS-EBG PPW reduces the radiated emission from -24 dB to -44 dB as compared to the conventional PPW.

• Journal of Power Electronics
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• v.9 no.2
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• pp.133-145
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• 2009

In this paper a modular high performance MV-to-LV rectifier based on a cascaded H-bridge rectifier is presented. The proposed rectifier can directly connect to the medium voltage levels and provide a low-voltage and highly-stable DC interface with the consumer applications. The input stage eliminates the necessity for heavy and bulky step-down transformers. It corrects the input power factor and maintains the voltage balance among the individual DC buses. The second stage includes the high frequency parallel-output DC/DC converters which prepares the galvanic isolation, regulates the output voltage, and attenuates the low frequency voltage ripple ($2f_{line}$) generated by the first stage. The parallel-output converters can work in interleaving mode and the active load-current sharing technique is utilized to balance the load power among them. The detailed analysis for modeling and control of the proposed structure is presented. The validity and performance of the proposed topology is verified by simulation and experimental results.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.19 no.39
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• pp.47-61
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• 1996

We propose a parallel neural network model in which patterns are clustered and patterns in a cluster are studied in a parallel neural network. The learning algorithm used in this paper is based on LVQ algorithm of Kohonen(1990) for clustering and ADALINE(Adaptive Linear Neuron) network of Widrow and Hoff(1990) for parallel learning. The proposed algorithm consists of two parts. First, N patterns to be learned are categorized into C clusters by LVQ clustering algorithm. Second, C patterns that was selected from each cluster of C are learned as input pattern of ADALINE(Adaptive Linear Neuron). Data used in this paper consists of 250 patterns of ASCII characters normalized into $8\times16$ and 1124. The proposed algorithm consists of two parts. First, N patterns to be learned are categorized into C clusters by LVQ clustering algorithm. Second, C patterns that was selected from each cluster of C are learned as input pattern of ADALINE(Adaptive Linear Neuron). Data used in this paper consists 250 patterns of ASCII characters normalized into $8\times16$ and 1124 samples acquired from signals generated from 9 car models that passed Inductive Loop Detector(ILD) at 10 points. In ASCII character experiment, 191(179) out of 250 patterns are recognized with 3%(5%) noise and with 1124 car model data. 807 car models were recognized showing 71.8% recognition ratio. This result is 10.2% improvement over backpropagation algorithm.