• Title/Summary/Keyword: Input signal

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Design of a 6-bit 500MS/s CMOS A/D Converter with Comparator-based Input Voltage Range Detection Circuit

  • Dae, Si;Yoon, Kwang Sub
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.14 no.6
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    • pp.706-711
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    • 2014
  • A low power 6-bit flash ADC that uses an input voltage range detection algorithm is described. An input voltage level detector circuit has been designed to overcome the disadvantages of the flash ADC which consume most of the dynamic power dissipation due to comparators array. In this work, four digital input voltage range detectors are employed and each input voltage range detector generates the specific clock signal only if the input voltage falls between two adjacent reference voltages applied to the detector. The specific clock signal generated by the detector is applied to turn the corresponding latched comparators on and the rest of the comparators off. This ADC consumes 68.82 mW with a single power supply of 1.2V and achieves 4.3 effective number of bits for input frequency up to 1 MHz at 500 MS/s. Therefore it results in 4.6 pJ/step of Figure of Merit (FoM). The chip is fabricated in 0.13-um CMOS process.

Effects of Input Harmonics, DC Offset and Step Changes of the Fundamental Component on Single-Phase EPLL and Elimination

  • Luo, Linsong;Tian, Huixin;Wu, Fengjiang
    • Journal of Power Electronics
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    • v.15 no.4
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    • pp.1085-1092
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    • 2015
  • In this paper, the expressions of the estimated information of a single-phase enhanced phase-locked loop (EPLL), when input signal contains harmonics and a DC offset while the fundamental component takes step changes, are derived. The theoretical analysis results indicate that in the estimated information, the nth-order harmonics cause n+1th-order periodic ripples, and the DC offset causes a periodic ripple at the fundamental frequency. Step changes of the amplitude, phase angle and frequency of the fundamental component cause a transient periodic ripple at twice the frequency. These periodic ripples deteriorate the performance of the EPLL. A hybrid filter based EPLL (HF-EPLL) is proposed to eliminate these periodic ripples. A delay signal cancellation filter is set at the input of the EPLL to cancel the DC offset and even-order harmonics. A sliding Goertzel transform-based filter is introduced into the amplitude estimation loop and frequency estimation loop to eliminate the periodic ripples caused by the residual input odd-order harmonics and step change of the input fundamental component. The parameter design rules of the two filters are discussed in detail. Experimental waveforms of both the conventional EPLL and the proposed HF-EPLL are given and compared with each other to verify the theoretical analysis and advantages of the proposed HF-EPLL.

Gain Characteristics of Fabry-Perot Type AlGaAs Semiconductor Laser Amplifier (Fabry-Perot 공진기형 AlGaAs 반도체 레이저 증폭기의 이득특성)

  • 김도훈;권진혁
    • Korean Journal of Optics and Photonics
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    • v.2 no.2
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    • pp.67-73
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    • 1991
  • The unsaturated signal gain, signal gain bandwidth, and saturation power which are important parameters determining characteristics of the semiconductor laser amplifier were measured for an AlGaAs Fabry-Perot cavity type laser amplifier and compared with the results of Fabry-Perot formula. The unsaturated signal gain 25 dB is obtained near oscillation thereshold current at $0.7\mu\textrmW$ input power. The corresponding signal gain bandwidth was about 3 GHz. Also. We measured the variation of the saturation signal gain and saturation power.

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HEARING AND HOWLING SUPPRESSION BY ADAPTIVE FEEDBACK CANCELLATION WITH FREQUENCY COMPRESSION

  • Harry Alfonso L. Joson;futoshi Asano;Yoiti Suzuki;Toshio Sone
    • Proceedings of the Acoustical Society of Korea Conference
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    • 1994.06a
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    • pp.919-924
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    • 1994
  • The use of adaptive feedback cancellation to prevent howling requires a reference signal that is correlated with the feedback signal by is not correlated with the input signal. Such a signal is hard to obtain in hearing aids. In this paper, the use fo frequency compression to decorrelate the output signal with input signal for use as reference is presented. Performance evaluation results indicate that with the proper choice of system parameters, the use of this system can provide a significant increase in howling margin with minimal deterioration in output signal quality.

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Experimental Evaluation of Frequency Characteristics of Gain-saturated EDFA for Suppression of Signal Fluctuation in Terrestrial Free-space Optical Communication Systems

  • Yoo Seok, Jeong;Chul Han, Kim
    • Current Optics and Photonics
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    • v.7 no.1
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    • pp.28-32
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    • 2023
  • Frequency characteristics of gain-saturated erbium-doped fiber amplifier (EDFA) are experimentally evaluated to mitigate the optical signal fluctuation induced by atmospheric turbulence in terrestrial freespace optical communication systems. Here, an acousto-optic modulator (AOM) is used to emulate optical signal fluctuations induced by atmospheric turbulence. The waveform which is generated in proportion to the refractive-index structural parameters is used to drive the AOM at various periodic frequencies. Thus, the dependence of the signal fluctuation suppression on the frequency is evaluated. The experiment is conducted using a periodic frequency sweep of the AOM driving voltage waveform and signal input power variation of the amplifier. It is observed that a low periodic frequency and high input signal power effectively suppress the optical signal fluctuation. This study evaluates the experimental results from the high-pass filter and gain-saturation characteristics of the EDFA.

A Study on Signal Processing Using Multiple-Valued Logic Functions (디치논리 함수를 이용한 신호처리 연구)

  • 성현경;강성수;김흥수
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.27 no.12
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    • pp.1878-1888
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    • 1990
  • In this paper, the input-output interconnection method of the multi-valued signal processing circuit using perfect Shuffle technique and Kronecker product is discussed. Using this method, the design method of circuit of the multi-valued Reed-Muller expansions(MRME) to be used the multi-valued signal processing on finite field GF(p**m) is presented. The proposed input-output interconnection method is shown that the matrix transform is efficient and that the module structure is easy. The circuit design of MRME on FG(p**m) is realized following as` 1) contructing the baisc gates on GF(3) by CMOS T gate, 2) designing the basic cells to be implemented the transform and inverse transform matrix of MRME using these basic gates, 3) interconnecting these cells by the input-output interconnecting method of the multivalued signal processing circuits. Also, the circuit design of the multi-valued signal processing function on GF(3\ulcorner similar to Winograd algorithm of 3x3 array of DFT (discrete fourier transform) is realized by interconnection of Perfect Shuffle technique and Kronecker product. The presented multi-valued signal processing circuits that are simple and regular for wire routing and posses the properties of concurrency and modularity are suitable for VLSI.

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Performance Analysis of MSAGF-MMA Adaptive Blind Equalization Algorithm with Variable Step Size Using Input Power Signal and Decision-Directed Error Signal (입력 전력 신호와 결정지향 오차 신호를 이용한 가변 스텝 크기를 가지는 MSAGF-MMA 적응 블라인드 등화 알고리즘의 성능 분석)

  • Jeong, Young-Hwa
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.20 no.3
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    • pp.53-58
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    • 2020
  • This paper is concerned with the performance analysis of MSAGF-MMA with variable step size whose step size varies according to input power signal and decision-directed error signal. The proposed algorithm is made to change according to the input power signal which can reliably increase the convergence speed to the steady state by making the step size less affected by the fluctuation of the input signal in the MMA having the binary flag obtained from the modified Stop-and-Go algorithm. At the same time, the step size can be varied according to the decision-directed error signal so that the residual error can be reduced in the steady state. As a result of computer simulations, it is confirmed that the proposed algorithm has a very good performance in the evaluation of residual ISI and averaged-MSE in steady state as well as in terms of convergence speed to steady state compared to MMA and MSAGF-MMA.

Design of Real-Time Adaptive Lattice Predictor Using (DSP를 이용한 실시간 적응격자 예측기 설계)

  • 김성환;홍기룡;홍완희
    • Journal of the Korean Institute of Telematics and Electronics
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    • v.25 no.2
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    • pp.119-124
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    • 1988
  • Real-time adaptive lattice predictor was implemented on the TMS32020 DSP chip for digital signal processing. The implemented system was composed of Input-Output units and centrla processing-control unit and its supporting assembly soft ware. The performance of hardware realization was verified by comparing input signal and one-step prediction signal which are calcualted by the real-time adaptive lattice predictor. As a result, for 4 stage lattice structure, the maximum running frequency was obtained as 6.41 KHz in this experiment.

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New Switching signal Pattern in AC Chopper (교류초퍼에서 새로운 스위칭 신호패턴)

  • Jang, Do-Hyun;Yeon, Jae-Eul
    • Proceedings of the KIEE Conference
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    • 2000.07b
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    • pp.1267-1269
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    • 2000
  • New switching signal pattern for four switches is proposed to prevent the shortage of PWM ac choppers. In the proposed technique, four signals to four power switches are generated without current transformer, while the conventional technique requires sensing the polarity of input voltage by voltage comparator and checking the direction of input current by the current transformer. The signal circuit built by the proposed technique is simple, and reduces also the switching loss.

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