• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.8 s.338
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• pp.43-52
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• 2005

An prescaler which uses PLL(Phase Locked Loop) must satisfy high speed operation and low power consumption. Thus the performance or TSPC(True Single Phase Clocked) D-flip flops which is applied at Prescaler is very important. Power consumption of conventional TSPC D-flip flops was increased with glitches from output and unnecessary discharge at internal node in precharge phase. We proposed a new D-flip flop which reduced two clock transistors for precharge and discharge Phase. With inserting a new PMOS transistor to the input stage, we could prevent from unnecessary discharge in precharge phase. Moreover, to remove the glitch problems at output, we inserted an PMOS transistor in output stage. The proposed flip flop showed stable operations as well as low power consumption. The maximum frequency of prescaler by applying the proposed D-flip flop was 2.92GHz and achieved power consumption of 10.61mw at 3.3V. In comparison with prescaler applying the conventional TSPC D-flip $flop^[6]$, we obtained the performance improvement of $45.4\%$ in the view of PDP(Power-Belay-Product).

• Journal of Korean Society of Transportation
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• v.20 no.4
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• pp.51-61
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• 2002

In this dissertation, We demonstrated the Travel Time forecasting model in the freeway of multi-section with regard of drives' attitude. Recently, the forecasted travel time that is furnished based on expected travel time data and advanced experiment isn't being able to reflect the time-lag phenomenon specially in case of long distance trip, so drivers don't believe any more forecasted travel time. And that's why the effects of ATIS(Advanced Traveler Information System) are reduced. Therefore, in this dissertation to forecast the travel time of the freeway of multi-section reflecting the time-lag phenomenon & the delay of tollgate, we used traffic volume data & TCS data that are collected by Korea Highway Cooperation. Also keep the data of mixed unusual to applicate real system. The applied model for forecasting is consisted of feed-forward structure which has three input units & two output units and the back-propagation is utilized as studying method. Furthermore, the optimal alternative was chosen through the twelve alternative ideas which is composed of the unit number of hidden-layer & repeating number which affect studying speed & forecasting capability. In order to compare the forecasting capability of developed ANN model. the algorithm which are currently used as an information source for freeway travel time. During the comparison with reference model, MSE, MARE, MAE & T-test were executed, as the result, the model which utilized the artificial neural network performed more superior forecasting capability among the comparison index. Moreover, the calculated through the particularity of data structure which was used in this experiment.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.37-45
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• 2004

As Internet technologies are mature, many new applications that are different characteristics are emerging. Recently we see wide use of P2P(Peer to Peer) applications of which traffic shows different statistical characteristics compared with traditional application such as web(HTTP) and FTP(File Transfer Protocol). In this paper, we measured subscriber network of KT(Korea Telecom) to analyze P2P traffic characteristics. We show flow characteristics of measured traffic. We also estimate Hurst parameter of P2P traffic and compare self-similarity with web traffic. Analysis results indicate that P2P traffic is much bustier than web traffic and makes both upstream traffic and downstream traffic be symmetric. To predict parameters related QoS such as packet loss and delays we model P2P traffic using two self-similar traffic models and predict both loss probability and mm delay then compare their accuracies. With simulation we show that the self-similar traffic models we derive predict the performance of P2P traffic accurately and thus when we design a network or evaluate its performance, we can use the P2P traffic model as reference input traffic.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.4
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• pp.80-89
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the$^1$costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that it fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs by 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.4
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• pp.2749-2756
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• 2015

Recently, Depending on the quality of data increases, the problem of time-consuming to process the image is raised by being required to accelerate the image processing algorithms, in a traditional CPU and CUDA(Compute Unified Device Architecture) based recognition system for computing speed and performance gains compared to OpenMP When character recognition has been learned by the system to measure the input by the character data matching is implemented in an environment that recognizes the region of the well, so that the font of the characters image learning English alphabet are each constant and standardized in size and character an image matching method for calculating the matching has also been implemented. GPGPU (General Purpose GPU) programming platform technology when using the CUDA computing techniques to recognize and use the four cores of Intel i5 2500 with OpenMP to deal quickly and efficiently an algorithm, than the performance of existing CPU does not produce the rate of four times due to the delay of the data of the partition and merge operation proposed a method of improving the rate of speed of about 3.2 times, and the parallel processing of the video card that processes a result, the sequential operation of the process compared to CPU-based who performed the performance gain is about 21 tiems improvement in was confirmed.

• Journal of Broadcast Engineering
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• v.22 no.1
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• pp.28-41
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• 2017

In this paper, the fast encoding algorithm in High Efficiency Video Coding (HEVC) encoder was studied. For the encoding efficiency, the current HEVC reference software is divided the input image into Coding Tree Unit (CTU). then, it should be re-divided into CU up to maximum depth in form of quad-tree for RDO (Rate-Distortion Optimization) in encoding precess. But, it is one of the reason why complexity is high in the encoding precess. In this paper, to reduce the high complexity in the encoding process, it proposed the method by determining the maximum depth of the CU using a hierarchical clustering at the pre-processing. The hierarchical clustering results represented an average combination of motion vectors (MV) on neighboring blocks. Experimental results showed that the proposed method could achieve an average of 16% time saving with minimal BD-rate loss at 1080p video resolution. When combined the previous fast algorithm, the proposed method could achieve an average 45.13% time saving with 1.84% BD-rate loss.

• Environmental and Resource Economics Review
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• v.19 no.2
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• pp.361-382
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• 2010

In 2005, the Korean government decided to postpone the introduction of competition up to 2009 in the power plant service industry. Thus, the purpose of this study is to analyze the efficiency changes and the determinants of international competitiveness of Korean power plant service industry by the comparison between before and after 2006. The sample used in the estimation of efficiency is six firms III Korean power plant service sector for the period of 2003~2008. According to the results, technical efficiency before 2006 (2003~2005) is 0.865 and that after 2005 (2006~2008) is 0.947, which implies that efficiency has been improved after the delay of introduction of competition. In addition, according to the analyses based on the diamond model of Porter using survey data, demand condition has been ranked first in the determinants of international competitiveness. The second and the third important conditions are government and input factor ones. Firm's strategy/structure/competitiveness condition is the most weak condition. Therefore, it would be necessary for firms to improve this condition for competitiveness.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.1 no.1
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• pp.41-51
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• 2002

As Advanced Traveler Information System(ATIS) is the kernel of the Intelligent Transportation System, it is very important how to manage data from traffic information collectors on a road and have at borough grip of the travel time's change quickly and exactly for doing its part. Link travel time can be obtained by two method. One is measured by area detection systems and the other is estimated by point detection systems. Measured travel time by area detection systems has the limitation for real time information because it Is calculated by the probe which has already passed through the link. Estimated travel time by point detection systems is calculated by the data on the same time of each. section, this is, it use the characteristic of the various cars of each section to estimate travel time. For this reason, it has the difference with real travel time. In this study, Artificial Neural Networks is used for estimating link travel time concerned about the relationship with vehicle detector data and link travel time. The method of estimating link travel time are classified according to the kind of input data and the Absolute value of error between the estimated and the real are distributed within 5$\~$15minute over 90 percent with the result of testing the method using the vehicle detector data and AVI data of Namsan Tunnel $\#$1. It also reduces Time lag of the information offered time and draws late delay generation and dissolution.

• The Transactions of the Korea Information Processing Society
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• v.7 no.1
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• pp.224-234
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• 2000

In this paper, we propose a new CPLD technology mapping algorithm for sequential circuit under time constraints. The algorithm detects feedbacks of sequential circuit, separate each feedback variables into immediate input variable, and represent combinational part into DAG. Also, among the nodes of the DAG, the nodes that the number of outdegree is more than or equal to 2 is not separated, but replicated from the DAG, and reconstructed to fanout-free-tree. To use this construction method is for reason that area is less consumed than the TEMPLA algorithm to implement circuits, and process time is improved rather than TMCPLD within given time constraint. Using time constraint and delay of device the number of partitionable multi-level is defined, the number of OR terms that the initial costs of each nodes is set to and total costs that the costs is set to after merging nodes is calculated, and the nodes that the number of OR terms of CLBs that construct CPLD is excessed is partitioned and is reconstructed as subgraphs. The nodes in the partitioned subgraphs is merged through collapsing, and the collapsed equations is performed by bin packing so that if fit to the number of OR terms in the CLBs of a given device. In the results of experiments to MCNC circuits for logic synthesis benchmark, we can shows that proposed technology mapping algorithm reduces the number of CLBs bu 15.58% rather than the TEMPLA, and reduces process time rather than the TMCPLD.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.5
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• pp.872-882
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• 1994

In this paper, the Low Noise Amplifier(LNA) is designed and fabricated to include a band pass filter characteristics considering the antenna system characteristics according to the transmitting and receiving signal level of communication satellite transponder. As an example, a 2-stage low noise amplifier and a 4-stage amplifier and designed, fabricated and measured at 14,0~14.5GHz of receiving frequency band. This fabricated LNA has shown the gain with very good flatness within pass-band, and its gain decreases rapidly out of band resulting in supperssion of the transmitting signal power leakage. It has shown the 20.3dB +- 0.1dB of pass-band gain, the 1.44dB +-0.04dB of noise figure and the 14dB rejection out of band(12.25~12.75GHz). The gain flatness, noise figure and group delay of this 2-stage LNA satisfactorily met the simulation results. And the fabricated 4-stage amplifier has shown the more than 42dB of pass-band gain, the +-0.25dB of flatness and the 28dB of the rejection effect for transmitting power leakage. The 2-stage LNA and 4-stage amplifier, in this paper, will bring a design margin for the input filter and also result in the system cost reduction.