• Journal of Electrical Engineering and Technology
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• 제9권6호
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• pp.2224-2236
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• 2014

The performance of an isolated high voltage full bridge converter is improved using a voltage doubler. In a conventional high voltage full bridge converter, the diode of the transformer secondary voltage undergoes a voltage spike due to the leakage inductance of the transformer and the resonance occurring with the parasitic capacitance of the diode. In addition, in the phase shift control, conduction loss largely increases from the freewheeling mode because of the circulating current. The efficiency of the converter is thus reduced. However, in the proposed converter, the high voltage dual converter consists of a voltage doubler because the circulating current of the converter is reduced to increase efficiency. On the other hand, in the proposed converter, an input current is distributed when using parallel input / serial output and the output voltage can be doubled. However, the voltages in the 2 serial DC links might be unbalanced due to line impedance, passive and active components impedance, and sensor error. Considering these problems, DC injection is performed due to the complementary operations of half bridge inverters as well as the disadvantage of the unbalance in the DC link. Therefore, the serial output of the converter needs to control the balance of the algorithm. In this paper, the performance of the conventional converter is improved and a balance control algorithm is proposed for the proposed converter. Also, the system of the 1.5[kW] PCS is verified through an experiment examining the operation and stability.

• 전자공학회논문지SC
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• 제39권5호
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• pp.43-50
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• 2002

다이오드 정류회로의 전류 파형을 향상시키기 위해서 배전압 다이오드 정류회로에 대한 새로운 동작원리를 제안하였다. 기존의 배전압 정류회로는 대용량 캐패시터를 이용하여 출력전압을 높였으나 제안한 회로는 소용량의 캐패시터와 리액터를 이용하기 때문에 출력전압은 높아지지 않지만 입력전류의 파형을 개선할 수 있다. 그리고 역률과 효율이 각각 97[%], 98[%]을 얻을 수 있다. 제안한 정류기는 고조파 규제값과 스위치가 서로 영향을 미치지 않고 다이오드와 인덕터 그리고 콘덴서로 구성된 비선형 임피턴스 회로이다. 또한 일반적인 펄스 폭 변조 인버터와 하프 펄스 폭 변조 인버터를 비교하여 설명하였으며 제안된 하프 펄스 폭 변조 인버터에 의해서 낮은 스위칭 손실과 오버슈팅을 제어할 수 있다.

• Journal of Power Electronics
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• 제12권4호
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• pp.623-631
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• 2012

In this paper, a digital controller design procedure is presented for single-phase voltage-doubler boost rectifiers (VDBR). The model derivation of the single-phase VDBR is performed in the s-domain. After that the simplified equivalent z-domain models are derived. These z-domain models are utilized to design the input current and the output dc-link voltage controllers. For the controller design in the z-domain, the traditional K-factor method is modified by considering the nature of the digital controller. The frequency pre-warping and anti-windup techniques are adapted for the controller design. By using the proposed method, the phase margin and the control bandwidth are accurately achieved as required by controller designers in a practical frequency range. The proposed method is applied to a 2.5 kVA single-phase VDBR for Uninterruptible Power Supply (UPS) applications. From the simulation and the experimental results, the effectiveness of the proposed design method has been verified.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2010년도 하계학술대회 논문집
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• pp.142-143
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• 2010

An active-clamped current-fed half-bridge converter for the high step-up application is proposed in this paper. The proposed converter is composed of active clamping snubber circuits and a voltage doubler rectifier. The operational principle, theoretical analysis, and design considerations are presented. To confirm the operation, features, and validity of the proposed circuit, the experimental result for a 200W, 24V input and 400V output prototype are presented.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2003년도 춘계전력전자학술대회 논문집(1)
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• pp.85-88
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• 2003

In this Paper, we report the experimental results of the Forward-flyback U-U converter with current doubler and synchronous rectifier. The experimental converter, that has a output voltage 3.3V, output current 20A, maximum power of 66W, switching frequency of 290kHz and input voltage range of 36-75V, has been successfully implemented. As a result, in the entire voltage range the measured full load efficiency was above 85$\%$, and the output voltage was regulated at 3.3V within $\pm3{\%}$ tolerance.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 B
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• pp.1044-1048
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• 2001

This paper proposes a nonlinear impedance circuit composed by diodes and inductors or capacitors. This circuit needs no control circuits and switches, and the impedance value is changed by the polarity of current or voltage. This paper presents one of these applications to improve the input current of capacitor input diode rectifiers. The rectifier using the nonlinear impedance circuit id constructed with four diodes and four capacitors in addition to the conventional rectifiers, that is, it has eight diodes and five capacitors, including a DC link capacitor. It makes harmonic components of the input current reduce and the power factor improve. A circuit design method is shown by experimentation and confirmed simulation. It explained that compared conventional pulse-width modulated (PWM)inverter with half pulse-width modulated (HPWM) inverter proposed HPWM inverter eliminated dead-time by lowering switching loss and holding over-shooting.

• Journal of Power Electronics
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• 제15권4호
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• pp.1131-1138
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• 2015

This study presents an input-powered high-efficiency interface circuit for energy harvesting systems, and introduces a zero standby power design to reduce power consumption significantly while removing the external power supply. This interface circuit is composed of two stages. The first stage voltage doubler uses a positive feedback control loop to improve considerably the conversion speed and efficiency, and boost the output voltage. The second stage active diode adopts a common-grid operational amplifier (op-amp) to remove the influence of offset voltage in the traditional comparator, which eliminates leakage current and broadens bandwidth with low power consumption. The system supplies itself with the harvested energy, which enables it to enter the zero standby mode near the zero crossing points of the input current. Thereafter, high system efficiency and stability are achieved, which saves power consumption. The validity and feasibility of this design is verified by the simulation results based on the 65 nm CMOS process. The minimum input voltage is down to 0.3 V, the maximum voltage efficiency is 99.6% with a DC output current of 75.6 μA, the maximum power efficiency is 98.2% with a DC output current of 40.4 μA, and the maximum output power is 60.48 μW. The power loss of the entire interface circuit is only 18.65 μW, among which, the op-amp consumes only 2.65 μW.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2011년도 추계학술대회
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• pp.169-170
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• 2011

PFC(Power Factor Correction) converters are commonly designed for CCM(Continuous Conduction Mode). However, DCM(Discontinuous Conduction Mode) appears in the input current near the ZCP(Zero Crossing Point) at light loads, resulting in input current distortion. It is caused by inaccurate average current values obtained in DCM. This paper studies a simple digital control scheme that can be operated in both CCM and DCM with minimal changes to the CCM average current control structure.

• Journal of electromagnetic engineering and science
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• 제14권1호
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• pp.25-30
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• 2014

This paper discusses the design of a high frequency Greinacher voltage multiplier as rectifier; it has a greater conversion efficiency and higher output direct current (DC) voltage at high power compared to a simple halfwave rectifier. Multiple diodes in the Greinacher voltage multiplier with distributed circuits consume excited power to the rectifier equally, thereby increasing the overall power capacity of the rectifier system. The proposed rectifiers are a Greinacher voltage doubler and a Greinacher voltage quadrupler, which consist of only diodes and distributed circuits for high frequency applications. For each rectifier, the RF-to-DC conversion efficiency and output DC voltage for each input power and load resistance are analyzed for the maximum conversion efficiency. The input power with maximum conversion efficiency of the designed Greinacher voltage doubler and quadrupler is 3 and 7 dB higher, respectively;than that of the halfwave rectifier.

• Journal of Power Electronics
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• 제12권2호
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• pp.249-257
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• 2012

An interleaved PWM converter is proposed to implement the features of zero voltage switching (ZVS), load current sharing and ripple current reduction. The proposed converter includes two ZVS converters with a common clamp capacitor. With the shared capacitor, the charge balance of the two interleaved parts is automatically regulated under input voltage and load variations. The active-clamping circuit is used to realize the ZVS turn-on so that the switching losses on the power switches are reduced. The ZVS turn-on of all of the switching devices is achieved during the transition interval. The interleaved pulse-width modulation (PWM) operation will reduce the ripple current and the size of the input and output capacitors. The current double rectifier (CDR) is adopted in the secondary side to reduce output ripple current so that the sizes of the output chokes and capacitor are reduced. The circuit configuration, operation principles and design considerations are presented. Finally experimental results based on a 408W (24V/17A) prototype are provided to verify the effectiveness of the proposed converter.