• The Journal of Korean Institute of Communications and Information Sciences
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• v.17 no.8
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• pp.779-788
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• 1992

The Input /output (I /0) subsystem is often the bottleneck in high performance computer system. Generally, system performance evaluation models were enhanced to include the effect of the I/0 system. In this paper, we modeled the terminal servers which are Indispensable devices In distribution of computer resources. We use M /M /1 Queueing model for find out the point of the system performance FIFO buffer sizes In the terminal server arc the Important fanctions of the system design and could be effected to the overall system functions. We have proposed the of optimal buffer sizes in the model of terminal server for increasing the system performance. We analizing the vatting time for terruanl server using Queueing model. and We find out the reference model result from simulation.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.12
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• pp.63-70
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• 2013

This paper describes a high PSRR low-dropout(LDO) linear regulator for wide frequency range without output-capacitor. Owing to both of the cascode compensation technique and the current buffer compensation technique in nested Miller compensation loop, the proposed LDO not only maintaines high stability but also achieves high PSRR over wide frequency range with reasonable on-chip capacitances. Since the external capacitor is removed by the proposed compensation techniques, the cost for pad is eliminated. The designed LDO works under the input voltage range from 2.5V to 4.5V and provides up to 10mA load current with the output voltage of 1.8V. The LDO was implemented with 0.18um CMOS technology and the area is 300um X 120 um. The measured power supply rejection ratio(PSRR) is -76dB and -43dB at DC and 1MHz, respectively. The operating current is 25uA.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1674-1683
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• 2003

The performance of a packet data multiplexer with stop­and­wait ARQ protocols under Markovian interruption is considered in this work It is assumed that the input process, into the system is Poisson process, and that the output channel is divided into a series of time slots and a data packet can be transmitted in a slot time. In this system the round­trip propagation delay is defined to be the frame time. It is modeled that the output channel can be blocked by some Markevian interruption, whose state change between the blocking and non­-blocking states is given by Markov process. The overall system has been analyzed by constructing a relationship, taking the Markovian interruption into account, about the buffer behavior between the successive frames of slots. The validity of this analytical results has been verified by computer simulation.

• IE interfaces
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• v.11 no.3
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• pp.23-40
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• 1998

In this paper, a method to determine the optimal configuration of operating policies in an integrated-automated manufacturing system using the Taguchi method and computer simulation experiments is presented. An integrated-automated manufacturing system called direct-input-output manufacturing system(DIOMS) is described. We only consider the operational aspect of the DIOMS. Four operating policies including input sequencing control, dispatching rule for the storage/retrieval(S/R) machine, machine center-based part type selection rule, and storage assignment policy are treated as design factors. The number of machine centers, the number of part types, demand rate, processing time and the rate of each part type, vertical and horizontal speed of the S/R machine, and the size of a local buffer in the machine centers are considered as noise factors in generating various manufacturing system environment. For the performance characteristics, mean flow time and throughput are adopted. A robust design experiment with inner and outer orthogonal arrays are conducted by computer simulation, and an optimal configuration of operating policies is presented which consists of a combination of the level of each design factor. The validity of the optimal configurations is investigated by comparing their signal-to-noise ratios with those obtained with full factorial designs.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.72-75
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• 2003

For the analog output buffer in the data driver for large size and high resolution TFT-LCDs, we proposed operational amplifier (op-amp) which contains newly developed transconductance-boosted input stage which enables the low-power consumption and the high slew-rate. The slew-rate and the quiescent current of the proposed op-amp are $6.1V/{\mu}sec$ and $8{\mu}A$, respectively.

• Journal of the Korean Institute of Telematics and Electronics
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• v.5 no.1
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• pp.13-25
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• 1968

A detailed analysis of the transistor wide-band feedback amplifiers using the hybrid-$\pi$ equivalent circuit has been made. It is considered both for the low freqnency and for the high frequency. The expressions of the gain, bandwidth. input impedance and output impedance have been presented. It is shown that a series feedback amplifier should be driven from the voltage source and should drive into the low resistance load, and a shunt feedback amplifier should be driven from the current source and should drive into the high resistance load. It is also shown that these stages can be coupled without use of the buffer stage or coupling transformer.

• Journal of Korea Society of Digital Industry and Information Management
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• v.8 no.1
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• pp.107-115
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• 2012

This paper proposes on the structure for reducing the circuit area and increasing the computation speed in implementing to hardware using the SEED algorithm of a 128-bit block cipher. SEED cipher can be implemented with S/W or H/W method. It should be important that we have minimize the area and computation time in H/W implementation. To increase the computation speed, we used the structure of the pipelined systolic array, and this structure is a simple thing without including any buffer at the input and output circuit. This circuit can record the encryption rate of 320 Mbps at 10 MHz clock. We have designed the circuit with the Verilog HDL coding showing the circuit performances in the figures and the table.

• ETRI Journal
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• v.25 no.4
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• pp.270-273
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• 2003

This paper presents a simple process to integrate thin-film inductors with a bottom NiFe magnetic core. NiFe thin films with a thickness of 2 to 3${\mu}m$ were deposited by sputtering. A polyimide buffer layer and shadow mask were used to relax the stress of the NiFe films. The fabricated double spiral thin-film inductor showed an inductance of 0.49${\mu}H$ and a Q factor of 4.8 at 8 MHz. The DC-DC converter with the monolithically integrated thin-film inductor showed comparable performances to those with sandwiched magnetic layers. We simplified the integration process by eliminating the planarization process for the top magnetic core. The efficiency of the DC-DC converter with the monolithic thin-film inductor was 72% when the input voltage and output voltage were 3.5 V and 6 V, respectively, at an operating frequency of 8 MHz.

• Journal of Advanced Marine Engineering and Technology
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• v.28 no.4
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• pp.603-610
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• 2004

Time delays are included in most of actual systems, and some of which are shown as time varying. To analyze the time varying time delay system in the time domain. a useful delay module to express the function as a tool is much helpful to get corresponding outputs under given conditions. A method is proposed here to design the algorithm of time delay module for simulation or control purposes, including the problems of initializing and reallocating data in buffer. After classifying the time varying time delay into the distributed mode and lumped mode, an object to describe delay module is configured and tested under the defined input signal and given time delay variation. The simulation results show that the output of module matches reasonably with the case of real system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.2
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• pp.291-297
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• 2006

This paper describes the architecture for reducing its size and increasing the computation rate in implementing the SEED algorithm of a 128-bit block cipher, and the result of the circuit design. In order to increase the computation rate, it is used the architecture of the pipelined systolic array. This architecture is a simple thing without involving any buffer at the input and output part. By this circuit, it can be recorded 320 Mbps encryption rate at 10 MHz clock. We designed the circuits with goals of the high-speed computations and the simplified structures.