• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW

• Journal of IKEEE
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• v.25 no.1
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• pp.156-167
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• 2021

In this paper, we propose a digital transceiver unit design for in-building of 5G optical repeaters that extends the coverage of 5G mobile communication network services and connects to a stable wireless network in a building. The digital transceiver unit for driving the proposed 5G optical repeater is composed of 4 blocks: a signal processing unit, an RF transceiver unit, an optical input/output unit, and a clock generation unit. The signal processing unit plays an important role, such as a combination of a basic operation of the CPRI interface, a 4-channel antenna signal, and response to external control commands. It also transmits and receives high-quality IQ data through the JESD204B interface. CFR and DPD blocks operate to protect the power amplifier. The RF transmitter/receiver converts the RF signal received from the antenna to AD, is transmitted to the signal processing unit through the JESD204B interface, and DA converts the digital signal transmitted from the signal processing unit to the JESD204B interface and transmits the RF signal to the antenna. The optical input/output unit converts an electric signal into an optical signal and transmits it, and converts the optical signal into an electric signal and receives it. The clock generator suppresses jitter of the synchronous clock supplied from the CPRI interface of the optical input/output unit, and supplies a stable synchronous clock to the signal processing unit and the RF transceiver. Before CPRI connection, a local clock is supplied to operate in a CPRI connection ready state. XCZU9CG-2FFVC900I of Xilinx's MPSoC series was used to evaluate the accuracy of the digital transceiver unit for driving the 5G optical repeater proposed in this paper, and Vivado 2018.3 was used as the design tool. The 5G optical repeater digital transceiver unit proposed in this paper converts the 5G RF signal input to the ADC into digital and transmits it to the JIG through CPRI and outputs the downlink data signal received from the JIG through the CPRI to the DAC. And evaluated the performance. The experimental results showed that flatness, Return Loss, Channel Power, ACLR, EVM, Frequency Error, etc. exceeded the target set value.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.12
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• pp.22-31
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• 2015

Recently, 3rd Generation Partnership Project (3GPP) has developed device-to-device (D2D) communication to cope with the explosively increasing mobile data traffic. The D2D communication uses sidelink based on single carrier-frequency division multiple access (SC-FMDA) due to its low peak-to-average power ratio (PAPR). In addition, demodulation reference signal (DMRS) is designed to support multiple input multiple output (MIMO). In this paper, we propose the DFT-based channel estimation scheme for sidelink in D2D communication. The proposed scheme uses the 2-Dimensional Minimum Mean Square Error (2-D MMSE) interpolation scheme for the user moving at a high speed. We perform the system level simulation based on 20MHz bandwidth of 3GPP LTE-Advanced system. Simulation results show that the proposed channel estimation scheme can improve signal-to-interference-plus-noise ratio (SINR), throughput and spectral efficiency of conventional scheme.

• Proceedings of the KIPE Conference
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• 2001.12a
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• pp.109-114
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• 2001

Photovoltaic systems normally use a maximum power point tracking (MPPT) technique to continuously deliver the highest possible power to the load when variations in the insolation and temperature occur. A simple method of tracking the maximum power points (MPPs) and forcing the boost converter system to operate close to these points is presented through deriving small-signal model and transfer function of boost converter. This paper aims at modeling boost converter including equivalent series resistance of input reservoir capacitor by state-space-averaging method. In the future, properly designed controller for compensation will be constructed for maximum photovoltaic power tracking control.

• Journal of Internet Computing and Services
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• v.23 no.3
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• pp.13-20
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• 2022

IEEE 802.11ay Wi-Fi is the next generation wireless technology and operates in mmWave band. It supports the MU-MIMO (Multiple User Multiple Input Multiple Output) transmission in which an AP (Access Point) can transmit multiple data streams simultaneously to multiple STAs (Stations). To this end, the AP should perform MU-MIMO beamforming training with the STAs. For efficient MU-MIMO beamforming training, it is important for the AP to estimate signal strength measured at each STA at which multiple beams are used simultaneously. Therefore, in the paper, we propose a deep learning-based link quality estimation scheme. Our proposed scheme estimates the signal strength with high accuracy by utilizing a deep learning model pre-trained for a certain indoor or outdoor propagation scenario. Specifically, to estimate the signal strength of the multiple concurrent beams, our scheme uses the signal strengths of the respective single beams, which can be obtained without additional signaling overhead, as the input of the deep learning model. For performance evaluation, we utilized a Q-D (Quasi-Deterministic) Channel Realization open source software and extensive channel measurement campaigns were conducted with NIST (National Institute of Standards and Technology) to implement the millimeter wave (mmWave) channel. Our simulation results demonstrate that our proposed scheme outperforms comparison schemes in terms of the accuracy of the signal strength estimation.

• 제어로봇시스템학회:학술대회논문집
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• 2003.10a
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• pp.2641-2647
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• 2003

Conventional DLLs estimate the delay times of satellite signals individually and feed back these measurements to the VCO independently. But VDLL estimates delay times and user position directly and then estimate the feedback term for VCO using the estimated position changes. In this process, input measurements are treated as vectors and these vectors are used for navigation. First advantage of VDLL is that noise is reduced in all of the tracking channels making them less likely to enter the nonlinear region and fall below threshold. Second is that VDLL can operate successfully when the conventional independent parallel DLL approach fails completely. It means that VDLL receiver can get enough total signal power to track successfully to obtain accurate position estimates under the same conditions where the signal strength from each individual satellite is so low or week that none of the individual scalar DLL can remain in lock when operating independently. To operate VDLL successfully, it needs to know the initial user dynamics and position and prevents total system from the divergence. The suggested integration method is to use the inertial navigation system to provide initial dynamics for VDLL and to maintain total system stable. We designed the GPS/INS integrated navigation system. This new type of integrated system contained the vector pseudorange format generation block, VDLL signal processing block, position estimation block and the conversion block from position change to delay time feedback term aided by INS.

• Journal of electromagnetic engineering and science
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• v.18 no.1
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• pp.20-28
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• 2018

The time synchronization of each sub-unit of a pulsed generator is important to generate an output high-power radio frequency (RF) signal. To obtain the time synchronization between an input RF signal fed by an external source and an electron beam produced by an electric pulse generator, the influence of different charging voltages on a delay and a rise time of the output pulse waveform in the electric pulse generator should be carefully considered. This paper aims to study the timing characteristics of the delay and the rise time as a function of different charging voltages with a peak value of less than -35 kV in the high-voltage pulse generator, including a trigger generator (TG) and a pulse-forming line (PFL). The simulation has been carried out to estimate characteristics in the time domain, in addition to their output high-voltage amplitude. Experimental results compared with those obtained by simulation indicate that the delay of the output pulses of the TG and PFL, which are made by controlling the external triggering signal with respect to different charging voltages, is getting longer as the charging voltage is increasing, and their rise times are inversely proportional to the amplitude of the charging voltage.

• Journal of the Korean Institute of Telematics and Electronics
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• v.25 no.10
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• pp.1263-1273
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• 1988

An adaptive nulling technique is presented to synthetically overcome the integrated problems associated with the conventional LMS array in the performances of jammer rejection, convergence rate, misadjustment, and reference signal generation. The proposed method is to remove the target signal from the array input and to eliminate the reference signal prior to minimization processing. The algorithm is constrained to the residue noise level in adaptive processor. Analysis shows effectiveness of the algorithm for coherent and/or incoherent interference rejection, wide dynamic range of convergence factor, rapid adaptation rate, and small mean square error. Simulation results confirm the theoretical prediction.

• ETRI Journal
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• v.45 no.5
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• pp.899-909
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• 2023

In mobile communication, the most exploratory technology of fifth generation is massive multiple input multiple output (MIMO). The minimum mean square error and zero forcing based linear detectors are used in multiuser detection for MIMO single-carrier frequency division multiple access (SCFDMA). When the received signal is detected and regularization sequence is joined in the equalization of spectral null amplification, these schemes experience an error performance and the signal detection assesses an inversion of a matrix computation that grows into complexity. Ordered successive interference cancelation (OSIC) detection is considered for MIMO SC-FDMA, which uses a posteriori information to eradicate these problems in a realistic environment. To cancel the interference, sorting is preferred based on signal-to-noise ratio and log-likelihood ratio. The distinctiveness of the methodology is to predict the symbol with the lowest error probability. The proposed work is compared with the existing methods, and simulation results prove that the defined algorithm outperforms conventional detection methods and accomplishes better performance with lower complication.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.40 no.3
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• pp.152-162
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• 2003

In this paper, Binary to Quaternary Converter(BQC), Quaternary to Binary Converter(QBC) and Quaternary inverter circuit, which is the basic logic gate, have been proposed based on voltage mode. The BQC converts the two bit input binary signals to one digit quaternary output signal. The QBC converts the one digit quaternary input signal to two bit binary output signals. And two circuits consist of Down-literal circuit(DLC) and combinational logic block(CLC). In the implementation of quaternary inverter circuit, DLC is used for reference voltage generation and control signal, only switch part is implemented with conventional MOS transistors. The proposed circuits are simulated in 0.35 ${\mu}{\textrm}{m}$ N-well doubly-poly four-metal CMOS technology with a single +3V supply voltage. Simulation results of these circuit show 250MHz sampling rate, 0.6mW power consumption and maintain output voltage level in 0.1V.