• 대한전자공학회논문지
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• 제8권4호
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• pp.7-16
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• 1971

쌍트란지스터 회로에 의하면 전류제어형의 부성저항소자가 가능하다. 이와같은 부성소자를 사용한 구형파발진회로의 바이어스전류에 신호파를 중첩함으로써 펄스폭변조회로를 구성하였다. 신호파가 정인 경우에는 한쪽의 트란지스터의 바이어스전류만을 증가시키고, 또 신호파가 부인 경우에는 다른 한쪽의 바이러스만을 증가시키는 방법을 채택하였다. 따라서 신호회로로서 일종의 전파정류회로의 변형을 채용하였다. 발진주기의 이론적해석과 회로정수결정의 설계지침을 구명하고 실험회로를 제시하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.53-56
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• 2001

With the ever increasing clock frequency and integration level of CMOS circuits, I/O(input/output) and interconnect issues are becoming a growing concern. In this thesis, we propose the 2.5Gbps high speed input driver This driver consists of four different blocks, which are the high speed serializer , PECL(pseudo emitter coupled logic) Line Driver, PLL(phase lock loop) and pre-emphasis signal generator. The proposed pre-emphasis block will compensate the high frequency components of the 2.5Gbps data signal. Using the pre-emphasis block, we can obtain 2.5Gbps data signal with differential peak to peak voltage about 900 m $V_{p.p}$ This driver structure is on fabrication in 2.5v/10.25um 1poly, 5metal CMOS process.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년도 제37회 하계학술대회 논문집 D
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• pp.1803-1804
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• 2006

The purpose of this paper is to implement a Labview based TFDR Real Time system through the instruments of Pci eXtensions for Instrumentation(PXI). The proposed load impedance measurement algorithm was verified by experiments via the implemented real time system. The TFDR real time system consisted of the reference signal design, signal generation, signal acquisition, algorithm execution and results display parts. To implement real time system, all of the parts wore programmed by the Labview which is one of graphical programming languages. In the application software implemented by the Labview we were able to design a suitable reference signal according to the length and frequency attenuation characteristics of the target cable and controled the arbitrary waveform generator(ZT500PXI) of the signal generation part and the digital storage oscilloscope(ZT430PXI) of the signal acquisition part. By using the TFDR real time system with the terminal resistor on the target cable, we applied to the load impedance measurements. In the proposed load impedance algorithm a normalized time-frequency cross correlation function and a cross time-frequency distribution function was employed to calculate the reflection coefficient and phase difference between the input and the reflected signals.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.971-974
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• 1999

A offset compensated class A bipolar second-generation current conveyor (CCII) for high-accuracy current-mode signal processing was proposed. The CCII adopts two diode-connection transistor between voltage input and voltage output to reduce offset voltage. Experiments show that the proposed CCII has offset voltage of 0.05 ㎷, input impedance of 2 Ω and the 3-㏈ cutoff frequency of 30 MHz when used a voltage amplifier. The power dissipation is 6 ㎷.

• 한국지능시스템학회논문지
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• 제24권5호
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• pp.457-461
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• 2014

생물학적 신경 세포의 모델링을 위한 펄스타입 실리콘 뉴런 회로를 $0.18{\mu}m$ CMOS 공정을 이용하여 반도체 집적회로로 설계하였다. 제안하는 뉴런 회로는 입력 전류신호를 위한 커패시터 입력단과, 출력 전압신호 생성을 위한 증폭단 및 펄스신호 초기화를 위한 MOS 스위치로 구성된다. 전압신호 입력을 전류신호 출력으로 변환하는 기능의 시냅스 회로는 몇 개의 PMOS와 NMOS 트랜지스터로 이루어지는 범프회로를 사용한다. 제안하는 뉴런 모델의 검증을 위하여, 2개의 뉴런과 시냅스가 직렬연결된 뉴런체인을 구성하여 SPICE 모의실험을 실시하였다. 모의실험 결과, 뉴런신호의 생성과 시냅스 전달특성의 정상적인 동작을 확인하였다.

• 전자공학회논문지C
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• 제34C권10호
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• pp.19-26
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• 1997

Novel class AB CMOS second-generation current conveyors (CCII) using 0.6.mu.m n-well CMOS process for high-frequency current-mode signal processing were developed. The CCII for low power operation consists of a class AB push-pull stage for the current input, a complementary source follower for the voltage input, and a cascode current mirror for the current output. In this architecture, the two input stages are coupled by current mirrors to reduce the current input impedance. Measurements of the fabricated CCII show that the current input impedance is 875.ohm. and the bandwidth of flat gain when used as a voltage amplifier extends beyond 4MHz. The power dissipation is 1.25mW and the active chip area is 0.2*0.15[mm$\^$2/].

• 한국정보통신학회논문지
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• 제17권5호
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• pp.1055-1063
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• 2013

전자파 내성 및 전자파 장해 측정을 위한 표준 전자파 발생 장치 중 하나인 CTL cell에서 두 개의 입력 단자에 동일 신호와 역위상 신호 입력에 따른 다양한 전계와 자계 발생에 대해 살펴보았다. 기본 공진주파수 TE011이 2.20GHz인 CTL cell을 이용하여 우세 전계장과 우세 자계장 조건에서 입력 전력의 변화에 따른 전계 특성, 측정 위치에 따른 전계 특성, 주파수 변화에 따른 전계 특성을 측정하였고, 이를 이용하여 CTL cell의 측정 영역에서의 동작 특성과 공진주파수의 영향을 받지 않고 사용 가능한 주파수 대역을 살펴보았다.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.278-279
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• 2017

The SCR AC voltage controller controls the magnitude of the output voltage by controlling the delay angle based on the zero-crossing points of the input AC voltage. This paper presents a method to generate digitally SCR gate signal by using AVR in order to minimize the effects of ripples or noises including AC input voltage. The validity of the proposed SCR gate signal generation technique is verified through experiment result.

• 정보저장시스템학회논문집
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• 제2권1호
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• pp.56-64
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• 2006

This paper proposes a new and simple input prediction method for robust servo system. A robust tracking control system for optical disk drives to reject disk runout was recently proposed based on both Coprime Factorization(CF) and Zero Phase Error Tracking(ZPET) control. The CF control system can be designed simply and systematically. Moreover, this system has not only stability but also robustness to parameter uncertainties and disturbance rejection capability. Since optical disk tracking servo systems can detect only racking error, it was proposed that the reference input signal for ZPET could be estimated from tracking errors. In this paper, we propose a new control structure for the ZPET controller. It requires less memory than the previously proposed method for the reference signal generation. Therefore, it is very effective in runout control. Furthermore, this method can be applied to defective optical disk like surface defects on disk. Numerical simulation and experimental result show the proposed method effective.

• 한국원자력학회:학술대회논문집
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• 한국원자력학회 1998년도 춘계학술발표회논문집(1)
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• pp.321-328
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• 1998

A controller and sensor fault tolerant system jot a steam generator is designed with fuzzy logic. A structure of the : proposed fault tolerant redundant system is composed of a supervisor and two fuzzy weighting modulators. A supervisor alternatively checks a controlled and a sensor induced performances to identify Which Part, a controller or a sensor, is faulty. In order to analyze controller induced performance both an error and a charge in error of the system output an chosen as fuzzy variables. The fuzzy logic jot a sensor induced performance uses two variables : a deviation between two sensor outputs and its frequency, Fuzzy weighting modulator generates an output signal compensated for faulty input signal. Simulations show that the : proposed fault tolerant control scheme jot a steam generator regulates welt water level by suppressing fault effect of either controllers or sensors. Therefore through duplicating sensors and controllers with the proposed fault tolerant scheme, both a reliability of a steam generator control and sensor system and that of a power plant increase even mote.