• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.825-831
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• 2016

In this paper, a transimpedance amplifier based on a new DC offset cancellation (DCOC) method is proposed for WCDMA/LTE applications. The proposed method applies a sample and hold mechanism to the conventional DCOC method with a DC feedback loop. It prevents the removal of information around the DC, so it avoids signal-to-noise ratio degradation. It also reduces area and power consumption. It was designed in a $0.13{\mu}m$ deep n-well CMOS technology and drew a maximum current of 1.58 mA from a 1.2 V supply voltage. It showed a transimpedance gain of $80dB{\Omega}$, an input-referred noise current lower than 0.9 pA/${\surd}$Hz, an out-of-band input-referred 3rd-order intercept point more than 9.5 dBm, and an output DC offset lower than 10 mV. Its area is $0.46mm{\times}0.48mm$.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.1578-1581
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• 2009

This work describes a power and area efficient switched-capacitor cyclic DAC for mobile display drivers. The proposed DAC can be simply implemented with one opamp two capacitors and several switches. Furthermore, the op-amp input referred offset is attenuated at the DAC output without additional offset cancellation circuitry. The operation of the cyclic DAC is verified through circuit level simulations.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.97-103
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• 2006

This paper presents the method of improving second order intermodulation distortion(IMD2) and dc-offset problems in down-conversion mixer. A simple analysis reveals the IMD2 and dc-offset can be eliminated by controlling the duty cycles of local oscillator(LO) inputs. A mixer with the proposed method has been simulated with a $0.13{\mu}m$ RF CMOS technology with 5% mismatch in the load resistance, the mixer shows 2.04dBm IIP2 and 22mnV input referred DC-offset. By controlling two duty cycles of LO inputs, IIP2 and DC-offset can be improved to 38.8dBm and $777{\mu}V$, respectively.

• 전기의세계
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• v.18 no.5
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• pp.12-19
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• 1969

The sensitivity of transistorized d.c. amplifiers is mainly limited by drift at operating point caused by ambient temperature changes. A chopper-type transistorized amplifier is necessary to obtain a high sensitivity without recourse to drift compensation which requires the adjustment of several balancing controls. A chopper-stabilized system consisting of an electro-mechanical chopper for input and output and a high-gain a.c. amplifier is designed and analyzed. The gain of the a.c. amplifier, expressed as the ratio of voltages, is larger than 80db in the band of 50C/S - 100KC/S. The complete system gives an open-loop gain of 68db at direct current. The offset voltage is 20.mu.V referred in input and the voltage drift at the input is less than 10.mu.V/hr at 25.deg.C. This type of amplifier would be useful for the high-gain transistorized d.c. amplifier for analog computers. Also, due to the high input impedance, it is suitable for amplification of signals from wide range of source impedances.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.47 no.3
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• pp.13-18
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• 2010

This work proposes and characterizes switched-capacitor type cyclic digital-to-analog converter for display data driving. The proposed digital-to-analog converter composes simple structure, and can be implemented for low-power, small area display driver ICs. By circuit level simulations, it is verified that the op-amp input referred offset is attenuated at the DAC output and the circuit performance is robust at 0.5% of capacitor mismatch.

• Transactions on Semiconductor Engineering
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• v.2 no.4
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• pp.1-7
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• 2024

This paper presents a methodology for the design and verification of a high-precision comparator using an analytical approach. The primary objective is to meet the performance of comparator by performing an initial design based on parameters derived from theoretical equations, and then analytically verifying performance metrics such as offset through transient Monte Carlo simulations. The transistor size can be then optimized by considering the trade-offs between parameters to design a comparator that ultimately meets the performance requirements. In this methodology, the correlation between device size, threshold voltage mismatch, and input offset voltage is validated through transient Monte Carlo simulations, confirming analytical results. This analysis also verifies the reliability of comparator performance, demonstrating the validity of the design. This study presents an analytical design technique for comparator design and is expected to contribute to the evaluation of performance and reliability.

• Journal of IKEEE
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• v.14 no.2
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• pp.51-57
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• 2010

A CMOS rail-to-rail high voltage buffer amplifier is proposed to drive the gamma correction reference voltage of large TFT LCD panels. It is operating by a single supply and only shows current consumption of 0.5mA at 18V power supply voltage. The circuit is designed to drive the gamma correction voltage of 8-bit or 10-bit high resolution TFT LCD panels. The buffer has high slew rate, 0.5mA static current and 1k$\Omega$ resistive and capacitive load driving capability. Also, it offers wide supply range, offset voltages below 50mV at 5mA constant output current, and below 2.5mV input referred offset voltage. To achieve wide-swing input and output dynamic range, current mirrored n-channel differential amplifier, p-channel differential amplifier, a class-AB push-pull output stage and a input level detector using hysteresis comparator are applied. The proposed circuit is realized in a high voltage 0.18um 18V CMOS process technology for display driver IC. The circuit operates at supply voltages from 8V to 18V.