• Journal of the Korean institute of surface engineering
• /
• v.54 no.3
• /
• pp.133-138
• /
• 2021

Ternary Ti-X-N coatings, where X = Al, Si, Cr, O, etc., have been widely used for machining tools and cutting tools such as inserts, end-mills, and etc. Ti-Al-N-O coatings were deposited onto silicon wafer and WC-Co substrates by a cathodic arc evaporation (CAE) technique at various negative substrate bias voltages. In this study, the influence of substrate bias voltages during deposition on the microstructure and mechanical properties of Ti-Al-N-O coatings were systematically investigated to optimize the CAE deposition condition. Based on results from various analyses, the Ti-Al-N-O coatings prepared at substrate bias voltage of -80 V in the process exhibited excellent mechanical properties with a higher compressive residual stress. The Ti-Al-N-O (-80 V) coating exhibited the highest hardness around 30 GPa and elastic modulus around 303 GPa. The improvement of mechanical properties with optimized bias voltage of -80 V can be explained with the diminution of macroparticles, film densification and residual stress induced by ion bombardment effect. However, the increasing bias voltage above -80 V caused reduction in film deposition rate in the Ti-Al-N-O coatings due to re-sputtering and ion bombardment phenomenon.

• Journal of the Korean Crystal Growth and Crystal Technology
• /
• v.10 no.6
• /
• pp.412-417
• /
• 2000

High electric field stressed trap distributions were investigated in the thin silicon oxide of polycrystalline silicon gate metal oxide semiconductor capacitors. The transient currents associated with the off time of stressed voltage were used to measure the density and distribution of high voltage stress induced traps. The transient currents were due to the discharging of traps generated by high stress voltage in the silicon oxides. The trap distributions were relatively uniform near both cathode and anode interface in polycrystalline silicon gate metal oxide semiconductor devices. The stress generated trap distributions were relatively uniform the order of $10^{11}$~$10^{12}$ [states/eV/$\textrm{cm}^2$] after a stress. The trap densities at the oxide silicon interface after high stress voltages were in the $10^{10}$~$10^{13}$ [states/eV/$\textrm{cm}^2$]. It was appeared that the transient current that flowed when the stress voltages were applied to the oxide was caused by carriers tunneling through the silicon oxide by the high voltage stress generated traps.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.14 no.10
• /
• pp.5148-5155
• /
• 2013

The induced voltage on the telecommunication cable generated by nearby electric railway system may bring about telecommunication errors and safety accidents. In order to reduce the induced voltage and to achieve communication reliability, the effect of the shield cables and the recent double-track railway systems on the inductive interference should be investigated. This paper analyzes the parameters which seriously influence the induced voltage on the telecommunication cables which run parallel with a AT-fed electric railway line, and provides a simulation-based approach to estimate the amount of the induced voltage. Simulation results indicate that the induced noise voltage generated by a double-track railway decreases by 18 % compared to that generated by a single-track railway, showing the screening effect by nearby track. The induced noise voltages on the 50%-shielded cable and 15%-shielded cable decrease to 1/8 and 1/15 of the induced voltage on the non-shielded cable, respectively. A meaningful shield effect is achieved and the induced voltage is minimized by the double-track railway and the shielded cable.

• Journal of Electrical Engineering and Technology
• /
• v.9 no.2
• /
• pp.406-414
• /
• 2014

Significant penetration of induction motor loads into residential neighborhood and commercial regions of local transmission systems at least partially determine a vulnerability to a fault induced delayed voltage recovery (FIDVR) event. Highly concentrated induction motor loads with constant torque could stall in response to low voltages associated with system faults. FIDVR is caused by wide spread stalling of small HVAC units (residential air conditioner) during transmission level faults. An under voltage load shedding scheme (UVLS) can be an effective component in a strategy to manage FIDVR risk and limit the any potential disturbance. Under Voltage Load Shedding take advantage of the plan to recovery the voltage of the system by shedding the load ways to alleviation FIDVR.

• Journal of the Korea Society for Simulation
• /
• v.30 no.2
• /
• pp.33-40
• /
• 2021

The situation of high-altitude electromagnetic pulses (HEMP) arises from high-altitude nuclear explosions. The HEMP situation can be simulated through the threat level investigation (TLI). In this paper, the induced voltage according to the antenna type of the tactical mobile radio communication system was measured and analyzed by TLI. Under the influence of HEMP, electronic equipment can be paralyzed or damaged. HEMP protection filters are commercially available for power lines and signal lines. However, commercialization of HEMP filters for antennas is insufficient, and even some of them exist for lightning protection. In order to make an appropriate HEMP protection filter according to the frequency and type of the antenna, the induced voltage was measured and the maximum induced voltage was analyzed through extrapolation. It was found that the measured induced voltage decreased as the frequency increased, such as in the HF, VHF and UHF bands of the measurement results.

• Journal of the Korea Academia-Industrial cooperation Society
• /
• v.21 no.11
• /
• pp.861-869
• /
• 2020

A dynamo set for a high-power induction motor drive is expensive and needs a long time to manufacture. Therefore, the development of a simulator that functions as the induction motor and load equipment is required. A load simulator of an inverter for a high-power three-phase induction motor consists of a reactor and three-phase PWM inverter. Therefore, it cannot simulate the dynamic characteristics of an induction motor and functions only as a load. In this paper, a real-time simulator is proposed to simulate a model of an induction motor and the load characteristics based on an LCL filter and three-phase PWM rectifier for a three-phase induction motor. The currents of a PWM inverter that simulate the stator currents of the motor are controlled by the inductor currents and capacitor voltages of the LCL filter. The capacitor voltages of the LCL filter simulate the induced voltages in the stator windings by the rotating rotor fluxes of the motor, and the capacitor voltages are controlled by the inductor currents and a PWM rectifier. The rotor currents, the stator and rotor flux linkages, the electromagnetic torque, the slip frequency, and the rotor speed are derived from the inverter currents and the motor parameters. The electrical and mechanical model characteristics and the operation of vector control were verified by MATLAB/Simulink simulation.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2002.07a
• /
• pp.232-235
• /
• 2002

An 150 kV gas cluster ion accelerator was fabricated and assessed. The change of surface morphology and surface roughness were examined by an atom force microscope (AFM) after irradiation of $CO_2$ gas clusters on Si (100) surfaces at the acceleration voltages of 50 kV. The density of hillocks induced by cluster ion impact was gradually increased with the dosage up to 5$\times$10$^{11}$ ions/$\textrm{cm}^2$. At the boundary of the ion dosage of 10$^{12}$ ions/$\textrm{cm}^2$, the density of the induced hillocks was decreased and RMS (root mean square) surface roughness was not deteriorated further. At the dosage of 5x10$^{13}$ ions/$\textrm{cm}^2$, the induced hillocks completely disappeared and the surface became very flat. In addition, the irradiated region was sputtered. $CO_2$ cluster ions are irradiated at the acceleration voltage of 25 kV to remove hillocks on indium tin oxide (ITO) surface and thus to attain highly smooth surfaces. $CO_2$ monomer ions are also bombarded on the ITO surface at the same acceleration voltage to compare sputtering phenomena. From the AFM results, the irradiation of monomer ions make the hillocks sharper and the surfaces rougher On the other hand, the irradiation of $CO_2$ cluster ions reduces the hight of hillocks and planarize the ITO surfaces. From the experiment of isolated cluster ion impact on the Si surfaces, the induced hillocks m high had the surfaces embossed at the lower ion dosages. The surface roughness was slightly increased with the hillock density and the ion dosage. At higher than a critical ion dosage, the induced hillocks were sputtered and the sputtered particles migrated in order to fill valleys among the hillocks. After prolonged irradiation of cluster ions, the irradiated region was very flat and etched.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.43 no.1 s.343
• /
• pp.1-8
• /
• 2006

In this paper, we suggested a new antenna structure for the RFID(Radio Frequency IDentification) reader. The conventional RFID reader uses a loop antenna. The central area of a loop antenna shows a low magnetic field strength, especially for the case of a large loop antenna diameter. We proposed a parallel-fed multiple loop antenna. Simulation and measurement were carried out for a single loop antenna, series-fed and parallel-fed multiple loop antennas. Simulation results show that we can obtain 0.40A/m, 0.68A/m, 1.98A/m of magnetic field strengths at the central point of a reader antenna for a single loop antenna, series-fed and parallel-fed multiple loop antennas, respectively. We measured the $79mm{\time}48mm$ tag area averaged induced voltages with applying 20Vp-p same source signals to reader antennas through the resistors. Measured tag area averaged induced voltages at the central point of a reader antennas were 0.76V, 1.45V, 4.04V for a single loop antenna series-fed and parallel-fed multiple loop antennas, respectively. The results show that we can get high induced voltage which can grantee a longer reading distance with a proposed parallel-fed multiple loop antenna.

• Journal of the Korean Vacuum Society
• /
• v.11 no.3
• /
• pp.151-158
• /
• 2002

Fabricated were ultra-shallow $p^+-n$ junctions on n-type Si(100) substrates using decaborane $(B_{10}H_{14})$ ion implantation. Decaborane ions were implanted at the acceleration voltages of 5 kV to 10 kV and at the dosages of $1\times10^{12}\textrm{cm}^2$.The implanted specimens were annealed at $800^{\circ}C$, $900^{\circ}C$ and $1000^{\circ}C$ for 10 s in $N_2$ atmosphere through a rapid thermal process. From the measurement of the implantation-induced damages through $2MeV^4 He^{2+}$ channeling spectra, the implanted specimen at the acceleration voltage of 15 kV showed higher backscattering yield than those of the bare n-type Si wafer and the implanted specimens at 5 kV and 10 kV. From the channeling spectra, the calculated thicknesses of amorphous layers induced by the ioin implantation at the acceleration voltages of 5 kV, 10 kV and 15 kV were 1.9 nm, 2.5 nm and 4.3 nm, respectively. After annealing at $800^{\circ}C$ for 10 s in $N_2$ atmosphere, most implantation-induced damages of the specimens implanted at the acceleration voltage of 10 kV were recovered and they exhibited the same channeling yield as the bare Si wafer. In this case, the calculated thickness of the amorphous layer was 0.98 nm. Hall measurements and sheet resistance measurements showed that the dopant activation increased with implantation energy, ion dosage and annealing temperature. From the current-voltage measurement, it is observed that leakage current density is decreased with the increase of annealing temperature and implantation energy.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.40 no.10
• /
• pp.32-38
• /
• 2003

This works reports the measurement and analysis results on the hot electron induced device degradation in Gate-All-Around SOI MOSFET's, which were fabricated using commercially available SIMOX material. It is observed that the worst-case condition of the device degradation in nMOSFETs is $V_{GS}$ = $V_{TH}$ due to the higher impact ionization rate when the parasitic bipolar transistor action is activated. It is confirmed that the device degradation is caused by the interface state generation from the extracted degradation rate and the dynamic transconductance measurement. The drain current degradation with the stress gate voltages shows that the device degradation of pMOSFETs is dominantly governed by the trapping of hot electrons, which are generated in drain avalanche hot carrier phenomena.r phenomena.