• Title/Summary/Keyword: Increase output voltage level

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Application of SFCL on Bus Tie for Parallel Operation of Power Main Transformers in a Fuel Cell Power Systems

  • Chai, Hui-Seok;Kang, Byoung-Wook;Kim, Jin-Seok;Kim, Jae-Chul
    • Journal of Electrical Engineering and Technology
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    • v.10 no.6
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    • pp.2256-2261
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    • 2015
  • In the power plant using high temperature fuel cells such as Molten Carbonate Fuel Cell(MCFC), and Solid Oxide Fuel Cell(SOFC), the generated electric power per area of power generation facilities is much higher than any other renewable energy sources. - High temperature fuel cell systems are capable of operating at MW rated power output. - It also has a feature that is short for length of the line for connecting the interior of the generation facilities. In normal condition, these points are advantages for voltage drops or power losses. However, in abnormal condition such as fault occurrence in electrical system, the fault currents are increased, because of the small impedance of the short length of power cable. Commonly, to minimize the thermal-mechanical stresses on the stack and increase the systems reliability, we divided the power plant configuration to several banks for parallel operation. However, when a fault occurs in the parallel operation system of power main transformer, the fault currents might exceed the interruption capacity of protective devices. In fact, although the internal voltage level of the fuel cell power plant is the voltage level of distribution systems, we should install the circuit breakers for transmission systems due to fault current. To resolve these problems, the SFCL has been studied as one of the noticeable devices. Therefore, we analyzed the effect of application of the SFCL on bus tie in a fuel cell power plants system using PSCAD/EMTDC.

Development of 50kW High Efficiency Modular Fast Charger for Both EV and NEV (EV와 NEV 겸용 50kW급 고효율 모듈형 급속충전기 개발)

  • Kim, Min-Jae;Kim, Yeon-Woo;Prabowo, Yos;Choi, Se-Wan
    • The Transactions of the Korean Institute of Power Electronics
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    • v.21 no.5
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    • pp.373-380
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    • 2016
  • In this paper, a 50-kW high-efficiency modular fast charger for both electric vehicle (EV) and neighborhood electric vehicle (NEV) is proposed. The proposed fast charger consists of five 10-kW modules to achieve fault tolerance, ease of thermal management, and reduce component stress. Three-level topologies for both AC-DC and DC-DC converters are employed to use 600V MOSFET, resulting in ease of component selection and increase in switching frequency. The proposed three-level DC-DC converter with coupled inductor and its hybrid switching method can reduce the circulating current under wide output voltage range. A 50-kW prototype of the proposed fast charger was developed and tested to verify the validity of the proposed concept. Experimental results show that the proposed fast charger achieves a rated efficiency of 95.2% and a THD of less than 3%.

A Study on Double Band Hysteresis Current Control based on 3-Level Inverter to reduce the harmonic component in output current of FACTS devices (FACTS 기기의 고조파 저감을 위한 이중밴드 히스테리시스 전류 제어에 관한 연구)

  • Choi, Won-Kyoung;Choi, Jeong-Hye;Kim, Bum-Sik;Shin, Eun-Chul;Lee, Sang-Bin;Yoo, Ji-Yoon
    • Proceedings of the KIEE Conference
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    • 2005.04a
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    • pp.180-182
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    • 2005
  • The current control using a conventional hysteresis controller of a STATCOM based on two level VSI (Voltage Source Inverter) has high switching frequency and variable modulation frequency. This will increase the switching loss. In addition, the current error is not strictly limited So, in this paper to reduce the switching frequency and to maintain the constant modulation frequency, a novel double band hysteresis current controller based on 3-level VSI is proposed. A conventional hysteresis current control and a novel hysteresis current control was tested with digital simulation and verified the advantage of the novel hysteresis current controller.

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Proposal of Potted Inductor with Enhanced Thermal Transfer for High Power Boost Converter in HEVs

  • You, Bong-Gi;Ko, Jeong-Min;Kim, Jun-Hyung;Lee, Byoung-Kuk
    • Journal of Electrical Engineering and Technology
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    • v.10 no.3
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    • pp.1075-1080
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    • 2015
  • A hybrid electric vehicle (HEV) powertrain has more than one energy source including a high-voltage electric battery. However, for a high voltage electric battery, the average current is relatively low for a given power level. Introduced to increase the voltage of a HEV battery, a compact, high-efficiency boost converter, sometimes called a step-up converter, is a dc-dc converter with an output voltage greater than its input voltage. The inductor occupies more than 30% of the total converter volume making it difficult to get high power density. The inductor should have the characteristics of good thermal stability, low weight, low losses and low EMI. In this paper, Mega Flux® was selected as the core material among potential core candidates. Different structured inductors with Mega Flux® were fabricated to compare the performance between the conventional air cooled and proposed potting structure. The proposed inductor has reduced the weight by 75% from 8.8kg to 2.18kg and the power density was increased from 15.6W/cc to 56.4W/cc compared with conventional inductor. To optimize the performance of proposed inductor, the potting materials with various thermal conductivities were investigated. Silicone with alumina was chosen as potting materials due to the high thermo-stable properties. The proposed inductors used potting material with thermal conductivities of 0.7W/m·K, 1.0W/m·K and 1.6W/m·K to analyze the thermal performance. Simulations of the proposed inductor were fulfilled in terms of magnetic flux saturation, leakage flux and temperature rise. The temperature rise and power efficiency were measured with the 40kW boost converter. Experimental results show that the proposed inductor reached the temperature saturation of 107℃ in 20 minutes. On the other hand, the temperature of conventional inductor rose by 138℃ without saturation. And the effect of thermal conductivity was verified as the highest thermal conductivity of potting materials leads to the lowest temperature saturations.

Output Improvement of Two-dimensional Audio Actuators by Corona Surface Treatments to Increase Adhesive Properties of Piezoelectric Materials (코로나 표면 처리의 접착력 향상에 의한 이차원 오디오 시스템의 출력 개선)

  • Um, Kee-Hong
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.12 no.5
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    • pp.91-97
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    • 2012
  • Recently, the performances of electrical and electronic devices are improving while the sizes are becoming smaller. As sound-generating systems, the two-dimensional speakers have been developed in place of conventional three-dimensional ones. Piezoelectric materials show the mechanical vibrations due to the voltage applied from outside the materials. The early film speakers had a limitations of output power in that it was not easy to make the conducting macromolecular films on the surfaces of the materials due to the internal chemical properties of materials. We have adopted the corona surface treatment in order to improve the output characteristics by increasing the adhesion of the coating material on to the surface of the center material of piezo film. The results showed the improvement of output power in the wider range of operating frequencies.

An Integrated High Linearity CMOS Receiver Frontend for 24-GHz Applications

  • Rastegar, Habib;Ryu, Jee-Youl
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.16 no.5
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    • pp.595-604
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    • 2016
  • Utilizing a standard 130-nm CMOS process, a RF frontend is designed at 24 GHz for automotive collision avoidance radar application. Single IF direct conversion receiver (DCR) architecture is adopted to achieve high integration level and to alleviate the DCR problem. The proposed frontend is composed of a two-stage LNA and downconversion mixers. To save power consumption, and to enhance gain and linearity, stacked NMOS-PMOS $g_m$-boosting technique is employed in the design of LNA as the first stage. The switch transistors in the mixing stage are biased in subthreshold region to achieve low power consumption. The single balanced mixer is designed in PMOS transistors and is also realized based on the well-known folded architecture to increase voltage headroom. This frontend circuit features enhancement in gain, linearity, and power dissipation. The proposed circuit showed a maximum conversion gain of 19.6 dB and noise figure of 3 dB at the operation frequency. It also showed input and output return losses of less than -10 dB within bandwidth. Furthermore, the port-to-port isolation illustrated excellent characteristic between two ports. This frontend showed the third-order input intercept point (IIP3) of 3 dBm for the whole circuit with power dissipation of 6.5 mW from a 1.5 V supply.

Non-equal DC link Voltages in a Cascaded H-Bridge with a Selective Harmonic Mitigation-PWM Technique Based on the Fundamental Switching Frequency

  • Moeini, Amirhossein;Iman-Eini, Hossein;Najjar, Mohammad
    • Journal of Power Electronics
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    • v.17 no.1
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    • pp.106-114
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    • 2017
  • In this paper, the Selective Harmonic Mitigation-PWM (SHM-PWM) method is used in single-phase and three-phase Cascaded H-Bridge (CHB) inverters in order to fulfill different power quality standards such as EN 50160, CIGRE WG 36-05, IEC 61000-3-6 and IEC 61000-2-12. Non-equal DC link voltages are used to increase the degrees of freedom for the proposed SHM-PWM technique. In addition, it will be shown that the obtained solutions become continuous and without sudden changes. As a result, the look-up tables can be significantly reduced. The proposed three-phase modulation method can mitigate up to the 50th harmonic from the output voltage, while each switch has just one switching in a fundamental period. In other words, the switching frequency of the power switches are limited to 50 Hz, which is the lowest switching frequency that can be achieved in the multilevel converters, when the optimal selective harmonic mitigation method is employed. In single-phase mode, the proposed method can successfully mitigate harmonics up to the 50th, where the switching frequency is 150 Hz. Finally, the validity of the proposed method is verified by simulations and experiments on a 9-level CHB inverter.

A Design Of Cross-Shpaed CMOS Hall Plate And Offset, 1/f Noise Cancelation Technique Based Hall Sensor Signal Process System (십자형 CMOS 홀 플레이트 및 오프셋, 1/f 잡음 제거 기술 기반 자기센서 신호처리시스템 설계)

  • Hur, Yong-Ki;Jung, Won-Jae;Lee, Ji-Hun;Nam, Kyu-Hyun;Yoo, Dong-Gyun;Yoon, Sang-Gu;Min, Chang-Gi;Park, Jun-Seok
    • Journal of the Institute of Electronics and Information Engineers
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    • v.53 no.5
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    • pp.152-159
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    • 2016
  • This paper describes an offset and 1/f noise cancellation technique based hall sensor signal processor. The hall sensor outputs a hall voltage from the input magnetic field, which direction is orthogonal to hall plate. The two major elements to complete the hall sensor operation are: the one is a hall sensor to generate hall voltage from input magentic field, and the other one is a hall signal process system to cancel the offset and 1/f noise of hall signal. The proposed hall sensor splits the hall signal and unwanted signals(i.e. offset and 1/f noise) using a spinning current biasing technique and chopper stabilizer. The hall signal converted to 100 kHz and unwanted signals stay around DC frequency pass through chopper stabilizer. The unwanted signals are bloked by highpass filter which, 60 kHz cut off freqyency. Therefore only pure hall signal is enter the ADC(analog to dogital converter) for digitalize. The hall signal and unwanted signal at the output of an amplifer and highpass filter, which increase the power level of hall signal and cancel the unwanted signals are -53.9 dBm @ 100 kHz and -101.3 dBm @ 10 kHz. The ADC output of hall sensor signal process system has -5.0 dBm hall signal at 100 kHz frequency and -55.0 dBm unwanted signals at 10 kHz frequency.

A Preliminary Research on Optical In-Situ Monitoring of RF Plasma Induced Ion Current Using Optical Plasma Monitoring System (OPMS)

  • Kim, Hye-Jeong;Lee, Jun-Yong;Chun, Sang-Hyun;Hong, Sang-Jeen
    • Proceedings of the Korean Vacuum Society Conference
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    • 2012.02a
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    • pp.523-523
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    • 2012
  • As the wafer geometric requirements continuously complicated and minutes in tens of nanometers, the expectation of real-time add-on sensors for in-situ plasma process monitoring is rapidly increasing. Various industry applications, utilizing plasma impedance monitor (PIM) and optical emission spectroscopy (OES), on etch end point detection, etch chemistry investigation, health monitoring, fault detection and classification, and advanced process control are good examples. However, process monitoring in semiconductor manufacturing industry requires non-invasiveness. The hypothesis behind the optical monitoring of plasma induced ion current is for the monitoring of plasma induced charging damage in non-invasive optical way. In plasma dielectric via etching, the bombardment of reactive ions on exposed conductor patterns may induce electrical current. Induced electrical charge can further flow down to device level, and accumulated charges in the consecutive plasma processes during back-end metallization can create plasma induced charging damage to shift the threshold voltage of device. As a preliminary research for the hypothesis, we performed two phases experiment to measure the plasma induced current in etch environmental condition. We fabricated electrical test circuits to convert induced current to flickering frequency of LED output, and the flickering frequency was measured by high speed optical plasma monitoring system (OPMS) in 10 kHz. Current-frequency calibration was done in offline by applying stepwise current increase while LED flickering was measured. Once the performance of the test circuits was evaluated, a metal pad for collecting ion bombardment during plasma etch condition was placed inside etch chamber, and the LED output frequency was measured in real-time. It was successful to acquire high speed optical emission data acquisition in 10 kHz. Offline measurement with the test circuitry was satisfactory, and we are continuously investigating the potential of real-time in-situ plasma induce current measurement via OPMS.

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A Design of Wide-Bandwidth LDO Regulator with High Robustness ESD Protection Circuit

  • Cho, Han-Hee;Koo, Yong-Seo
    • Journal of Power Electronics
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    • v.15 no.6
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    • pp.1673-1681
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    • 2015
  • A low dropout (LDO) regulator with a wide-bandwidth is proposed in this paper. The regulator features a Human Body Model (HBM) 8kV-class high robustness ElectroStatic Discharge (ESD) protection circuit, and two error amplifiers (one with low gain and wide bandwidth, and the other with high gain and narrow bandwidth). The dual error amplifiers are located within the feedback loop of the LDO regulator, and they selectively amplify the signal according to its ripples. The proposed LDO regulator is more efficient in its regulation process because of its selective amplification according to frequency and bandwidth. Furthermore, the proposed regulator has the same gain as a conventional LDO at 62 dB with a 130 kHz-wide bandwidth, which is approximately 3.5 times that of a conventional LDO. The proposed device presents a fast response with improved load and line regulation characteristics. In addition, to prevent an increase in the area of the circuit, a body-driven fabrication technique was used for the error amplifier and the pass transistor. The proposed LDO regulator has an input voltage range of 2.5 V to 4.5 V, and it provides a load current of 100 mA in an output voltage range of 1.2 V to 4.1 V. In addition, to prevent damage in the Integrated Circuit (IC) as a result of static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class (Chip level) ESD protection circuit of a P-substrate-Triggered Silicon Controlled Rectifier (PTSCR) type with high robustness characteristics.