• Journal of Information Technology Applications and Management
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• v.13 no.2
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• pp.115-126
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. We propose a new transaction recovery scheme for a flash memory database environment which is based on a flash media file system. We improved traditional shadow paging schemes by reusing old data pages which are supposed to be invalidated in the course of writing a new data page in the flash file system environment. In order to reuse these data pages, we exploit deferred cleaning list structure in our flash memory shadow paging (FMSP) scheme. FMSP scheme removes the additional storage overhead for keeping shadow pages and minimizes the I/O performance degradation caused by data page distribution phenomena of traditional shadow paging schemes. We also propose a simulation model to show the performance of FMSP. Based on the results of the performance evaluation, we conclude that FMSP outperforms the traditional scheme.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.4
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• pp.274-282
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• 2016

This paper proposes code optimization techniques to reduce energy consumption of complex multimedia applications in a hybrid memory system with volatile dynamic random access memory (DRAM) and non-volatile spin-transfer torque magnetoresistive RAM (STT-MRAM). The proposed approach analyzes read/write operations for variables in an application. Based on the profile, variables with a high read operation are allocated to STT-MRAM, and variables with a high write operation are allocated to DRAM to reduce energy consumption. In this paper, to optimize code for real-life complicated applications, we develop a profiler, a code modifier, and compiler/link scripts. The proposed techniques are applied to a Fast Forward Motion Picture Experts Group (FFmpeg) application. The experiment reduces energy consumption by up to 22%.

• Proceedings of the KIEE Conference
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• 2006.04a
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• pp.267-269
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes.

• Journal of Information Technology Applications and Management
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• v.13 no.4
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• pp.257-271
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• 2006

Recently, flash memories are one of best media to support portable computer's storages in mobile computing environment. The features of non-volatility, low power consumption, and fast access time for read operations are sufficient grounds to support flash memory as major database storage components of portable computers. However, we need to improve traditional Indexing scheme such as B-Tree due to the relatively slow characteristics of flash operation as compared to RAM memory. In order to achieve this goal, we devise a new indexing scheme called F-Tree. F-Tree improves tree operation performance by compressing pointers and keys in tree nodes and rewriting the nodes without a slow erase operation in node insert/delete processes. Based on the results of the performance evaluation, we conclude that F-Tree indexing scheme outperforms the traditional indexing scheme.

• Journal of KIISE:Computing Practices and Letters
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• v.11 no.4
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• pp.305-311
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• 2005

Flash memory software running on cellular phones and PDAs need to be tested extensively to cope with abrupt power and media faults. For those tests, we designed and implemented a Flash memory emulator with fault injection features. The fault injection tester has provided a helpful framework for designing fault recovery schemes and also for analyzing fault damages to the FTL (Flash Translation Layer) and file system for a Flash memory based system. In this paper, we discuss Plash memory fault types and fault injection features implemented on this Flash memory emulator. We then discuss in detail a design flaw revealed during fault injection tests. Specifically, it was revealed that a scheme that was believed to improve reliability instead, turned out to be harmful. In addition, we discuss post-fault behaviors of the FTL and the file system.

• Journal of KIISE:Computing Practices and Letters
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• v.16 no.2
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• pp.177-185
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• 2010

Ray-object intersection is an important element in ray tracing that takes up a substantial amount of computing time. In general, such spatial data structure as kd-tree has been frequently used for static scenes to accelerate the intersection computation. Recently, a few variants of kd-tree traversal have been proposed suitable for the GPU that has a relatively restricted computing architecture compared to the CPU. In this article, we propose yet another two implementation techniques that can improve those previous ones. First, we present a cached stack method that is aimed to reduce the costly global memory access time needed when the stack is allocated to global memory. Secondly, we present a rope-with-short-stack method that eases the substantial memory requirement, often necessary for the previous rope method. In order to show the effectiveness of our techniques, we compare their performances with those of the previous GPU traversal methods. The experimental results will provide prospective GPU ray tracer developers with valuable information, helping them choose a proper kd-tree traversal method.

• KIISE Transactions on Computing Practices
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• v.23 no.7
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• pp.428-433
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• 2017

Recently, the demand for high performance non-volatile memory storage devices that can replace existing hard disks has been increasing in environments requiring high performance computing such as data-centers and social network services. The performance of such non-volatile memory can greatly depend on the interface between the host and the storage device. With the evolution of storage interfaces, the non-volatile memory express (NVMe) interface has emerged, which can replace serial attached SCSI and serial ATA (SAS/SATA) interfaces based on existing hard disks. The NVMe interface has a higher level of scalability and provides lower latency than traditional interfaces. In this paper, an evaluation and analysis are conducted of the performance of NVMe storage devices through various workloads. We also compare and evaluate the cost efficiency of NVMe SSD and SATA SSD.

• Journal of the Korea Society of Computer and Information
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• v.27 no.7
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• pp.9-16
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• 2022

Today, with the advent of the 4th industrial revolution, IoT (Internet of Things) systems are advancing rapidly. For this reason, a various application with high-performance and large-capacity are emerging. Therefore, there is a need for low-power and high-performance memory for computing systems with these applications. In this paper, we propose an effective structure for the L1 cache memory, which consumes the most energy in the computing system. The proposed cache system is largely composed of two parts, the L1 main cache and the buffer cache. The main cache is 2 banks, and each bank consists of a 2-way set association. When the L1 cache hits, the data is copied into buffer cache according to the proposed algorithm. According to simulation, the proposed L1 cache system improved the performance of energy delay products by about 65% compared to the existing 4-way set associative cache memory.

• 전기의세계
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• v.23 no.1
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• pp.61-68
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• 1974

This paper attempts to develop the algorithms and computer program for load flow solution and faults analysis of large power system by small digital computer. The Conventional methods for load flow solution and fault analysis of large power system require too much amount of computer memory space and computing time. Therefore, this paper describes the methad for reducing the computer memory space and computing time as follows. (1) Load Flow Solution; This method is to store each primitive impedance of lines along with a list of bus numbers corresponding to the both terminals of lines, and to store only nonzero element of bus admittance matrix. (2) Faults Analysis: This method is to partition a large power system into several groups of subsystems, form individual bus impedance matrix, store them in the storage, and assemble the only required portion of them to original total system by algorithm.

• Transactions of the Korean Society of Mechanical Engineers B
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• v.26 no.11
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• pp.1521-1530
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• 2002

This article proposes a pressure based method for predicting flows at all speeds. The compressible SIMPLE algorithm is extended to unstructured grid framework. Convection terms are discretized using second-order scheme with deferred correction approach. Diffusion term discretization is based on structured grid analogy that can be easily adopted to hybrid unstructured grid solver. This method also uses node centered scheme with edge based data structure for memory and computing time efficiency of arbitrary grid types. Both incompressible and compressible benchmark problems are solved using the above methodology. The demonstration of this method is extended to slip flow problem that has low Reynolds number but compressibility effect. It is shown that the proposed method can improve efficiency in memory usage and computing time without losing any accuracy.