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http://dx.doi.org/10.9708/jksci.2022.27.07.009

Designing a low-power L1 cache system using aggressive data of frequent reference patterns  

Jung, Bo-Sung (Dept. of Control&Instrument Engineering, Gyeongsang National University)
Lee, Jung-Hoon (Dept. of Control&Instrument Engineering, Gyeongsang National University)
Publication Information
Journal of the Korea Society of Computer and Information / v.27, no.7, 2022 , pp. 9-16 More about this Journal
Abstract
Today, with the advent of the 4th industrial revolution, IoT (Internet of Things) systems are advancing rapidly. For this reason, a various application with high-performance and large-capacity are emerging. Therefore, there is a need for low-power and high-performance memory for computing systems with these applications. In this paper, we propose an effective structure for the L1 cache memory, which consumes the most energy in the computing system. The proposed cache system is largely composed of two parts, the L1 main cache and the buffer cache. The main cache is 2 banks, and each bank consists of a 2-way set association. When the L1 cache hits, the data is copied into buffer cache according to the proposed algorithm. According to simulation, the proposed L1 cache system improved the performance of energy delay products by about 65% compared to the existing 4-way set associative cache memory.
Keywords
low-power system; L1 cache memory; Memory Characteristics; buffer system; replacement policy;
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