• Journal of the Korean Society for Nondestructive Testing
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• v.26 no.3
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• pp.190-197
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• 2006

For enhancement of flaw detactability using array transducers, focusing of ultrasonic waves on a target in an inhomogeneous medium or through a complex geometry is important. But focusing can be strongly degraded by geometrical distortion of field radiated by the array transducers or by sound speed fluctuations in the propagating medium. In recent years, the time reversal technique has been proposed. Thus, in this paper, we describe the basic principal of the time reversal technique for focusing. Then, the implementation results of the time reversal technique for ultrasonic inspections using bulk waves and guided waves generated by array transducers are presented.

• Journal of the Korean Institute of Telematics and Electronics
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• v.21 no.1
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• pp.25-31
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• 1984

An algorithm on time limited signal extrapolation technique is presented where the total extrapolation process of iteration method is achieved by a single matrix operation. The proposed technique and its implementation has many advantages over iteration method in terms of computational saving and accuracy of the results. As an examples in this paper, appling the proposed technique to ultrasonic diagnosis-device, we prove the excellence of the proposed technique.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.7B
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• pp.737-743
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• 2002

It is an essential design process to analyze the performance of Synthetic Aperture Radar (SAR) processor before implementation. The contribution of this paper is to identify the chief sources and types of errors, to assess their impact on system performance, and to suggest the analysis technique for principal performance of the space-based SAR processor using Range-Doppler Algorithm (RDA). Also, simulation is performed by the Experimental-SAR (E-SAR) processor to examine the practicability and efficiency of the technique, the results are discussed, and solutions for the problems are recommended. Therefore, this technique can be used to analyze the performance of the space-based SAR processor using RDA.

• IE interfaces
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• v.11 no.2
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• pp.149-157
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• 1998

In this paper, various techniques considering the characteristics of computer memory management are suggested, which can be used in the implementation of simplex method. First, reduction technique of indirect addressing, redundant references of memory, and scatter/gather technique are implemented, and the effectiveness of the techniques is shown. Loop-unrolling technique, which exploits the arithmetic operation mechanism of computer, is also implemented. Second, a subroutine frequently called is written in low-level language, and the effectiveness is proved by experimental results. Third, row-column linked list and Gustavson's data structure are compared as the data structure for the large sparse matrix in LU form. Last, buffering technique and memory-mapped file which can be used in reading large data file are implemented and the effectiveness is shown.

• ETRI Journal
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• v.40 no.6
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• pp.774-787
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• 2018

Arabic handwriting segmentation and recognition is an area of research that has not yet been fully understood. Dealing with Arabic ligature segmentation, where the Arabic characters are connected and unconstrained naturally, is one of the fundamental problems when dealing with the Arabic script. Arabic character-recognition techniques consider ligatures as new classes in addition to the classes of the Arabic characters. This paper introduces an enhanced technique for Arabic handwriting recognition using the deep belief network (DBN) and a new morphological algorithm for ligature segmentation. There are two main stages for the implementation of this technique. The first stage involves an enhanced technique of the Sari segmentation algorithm, where a new ligature segmentation algorithm is developed. The second stage involves the Arabic character recognition using DBNs and support vector machines (SVMs). The two stages are tested on the IFN/ENIT and HACDB databases, and the results obtained proved the effectiveness of the proposed algorithm compared with other existing systems.

• ETRI Journal
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• v.27 no.5
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• pp.557-562
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• 2005

Low-density parity-check (LDPC) codes have recently emerged due to their excellent performance. However, the parity check (H) matrices of the previous works are not adequate for hardware implementation of encoders or decoders. This paper proposes a hybrid parity check matrix which is efficient in hardware implementation of both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the proposed methods, the implementation of encoders can become practical while keeping the hardware complexity of the partly parallel decoder structures. An encoder and a decoder are designed using Verilog-HDL and are synthesized using a $0.35 {\mu}m$ CMOS standard cell library.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.6
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• pp.944-953
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• 1990

This paper describes design and implementation of a real-time high-precision vision system for an automation of SMT(surface mounting technology ). Also, a part inspection algorithm which calculates the position and direction of SMD(surface mounted device) accurately and performs the ruling using those information are presented, and a parallel processing technique for implementing those algorithms is also described. For a real-time implementation of iage acquisition and processing, several hardware modules, namely, multi-functional A/D-D/A board, frame memory board are developed. Particularly, a PE (processing element) board which employs the DSP56001 DSP (digital signal processor) is developed for the purpose of concurrent processing of part inspection algorithms. A stand-alone vision system is built by integration of the developed hardware modules and related softwares.

• 한국전산유체공학회:학술대회논문집
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• 1997.10a
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• pp.23-28
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• 1997

A parallel implementation is made of a two-dimensional finite volume model based on the SIMPLER. The solution domain is decomposed into several subdomains and the solution at each subdomain is acquired by parallel use of multiple processors. Communications between processors are accomplished by using the standard MPI and the Cray-specific SHMEM. The parallelization method for the overall solution procedure to the Navier-Stokes equations is described in detail, The parallel implementation is validated on the Cray T3E system for a benchmark problem of natural convection in a sidewall-heated cavity. The parallel performance is assessed and the issues encountered in achieving a high-performance parallel model are elaborated.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.53 no.9
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• pp.657-662
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• 2004

The low-power design of the digital hearing aid is indispensable to achieve the compact portable device with long battery duration. In this paper, new low-power adaptive filter structure is proposed based on distributed arithmetic(DA). By modifying the DA technique, the proposed decimation filter structure can significantly reduce the power consumption and implementation area. Through Verilog-HDL coding, cell occupation of the proposed structure is reduced to 33.49% in comparison with that of the conventional multiplier structure. Since Verilog-HDL simulation processing time of the two structures are same, it is assumed that the power consumption or implementation area is proportional to the cell occupation in the simulation.

• Journal of Korea Society of Digital Industry and Information Management
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• v.13 no.3
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• pp.35-42
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• 2017

This paper presents hardware implementation of background timing-skew calibration technique for time-interleaved analog-to-digital converters (TI ADCs). The timing skew between any two adjacent analog-digital (A/D) channels is detected by using pure digital Finite Impulse Response (FIR) delay filter. This paper includes hardware architecture of the system, main units and small sub-blocks along with control logic circuits. Moreover, timing diagrams of logic simulations using ModelSim are provided and discussed for further understanding about simulations. Simulation process in MATLAB and Verilog is also included and provided with basic settings need to be done. For hardware implementation it not practical to work with all samples. Hence, the simulation is conducted on 512 TI ADC output samples which are stored in the buffer simultaneously and the correction arithmetic is done on those samples according to the time skew algorithm. Through the simulated results, we verified the implemented hardware is working well.