• 한국조명전기설비학회지:조명전기설비
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• 제9권5호
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• pp.57-63
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• 1995

본 연구는 상전류가 상전압과 동위상에 가까운 정현파가 되도록 제어함으로써 배전선로의 고조파성분과 무효전력을 감소시킬 수 있는 3상 PWM AC/DC승압형 콘버터를 해석하고 안정된 제어방법을 제안하였다. 제어기의 실현에 있어서는 전류센서가 없는 순시전압 제어방식의 비교적 간단한 제어알고리즘을 도출하였고 순시전압 제어는 PWM방식을 아용하였다. 또한 스위칭손실을 줄이기 위하여 스위칭 주파수는 비교적 낮은 범위인 3[kHz]정도로 하였다. 부하가 능동부하일 경우 전원쪽으로 잉여전력의 회수가 가능한 4상한 동작 콘버터를 구성하였으며, 본 제어방식의 타당성을 시뮬레이션 및 실험을 통하여 확인 하였다.

• 한국산업정보학회논문지
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• 제21권4호
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• pp.21-30
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• 2016

In a single-phase power factor correction (PFC), the standard cascaded control algorithm using a proportional-integral-derivative (PID) controller has two main drawbacks: an inability to track sinusoidal current reference and low harmonic compensation capability. These drawbacks cause poor power factor and high harmonics in grid current. To improve these drawbacks, this paper uses a proportional-integral-derivative-resonant (PIDR) controller which combines a type-III PID with proportional-resonant (PR) controllers in the PFC. Based on a small signal model of the PFC, the type-III PID controller was implemented taking into account the bandwidth and phase margin of the PFC system. To adopt the PR controllers, the spectrum of inductor current of the PFC was analyzed in frequency domain. The hybrid PIDR controller were simulated using PSCAD/EMTDC and implemented on a 3 kW PFC prototype hardware. The performance results of the hybrid PIDR controller were compared with those of an individual type-III PID controller. Both controllers were implemented successfully in the single-phase PFC. The total harmonic distortion of the proposed controller were much better than those of the individual type-III PID controller.

• 전력전자학회논문지
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• 제20권6호
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권3호
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• 전기전자학회논문지
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• 제21권3호
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• pp.240-243
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• 2017

차량 내부의 전자 장치가 급증함에 따라 CAN(controller area network)에 데이터 병목 현상이 발생하기 시작했다. 이에 따라 CAN을 개량한 CAN-FD(CAN with flexible data rate) 버스가 개발되었는데, 버스 중재 단계(arbitration phase)에서는 CAN과 동일한 속도로 전송하되 데이터 전송 단계(data phase)에서는 훨씬 빠른 속도로 전송함으로서 호환성과 효율성을 모두 높였다. 본 논문에서는 CAN-FD 규격 1.0과 CAN 규격 2.0A, 2.0B를 모두 만족하는 CAN-FD 제어기를 Verilog HDL를 사용하여 설계하고 FPGA로 구현한 뒤 동작을 검증하였다. 0.18um 공정을 사용하여 합성한 결과는 약 46,300 게이트이다.

• Journal of Electrical Engineering and Technology
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• 제13권5호
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• Journal of Power Electronics
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• 제9권1호
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• pp.74-84
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• 2009

The design and implementation of a high performance PID (Proportional Integral & Differential) style controller with zero-phase error tracking property is considered in this article. Unlike a ball screw driven system, the controller in a direct drive system should provide a high level of tracking performance while avoiding the problems due to the absence of the gear system. The stiff mechanical element in a direct drive system allows high precise positioning capability, but relatively high tracking ability with minimal position error is required. In this work, a feasible position controller named 'Unified PID controller' is presented. It will be shown that the function of the closed position loop can be designed into unity gain system in continuous time domain to provide minimal position error. The focus of this work is in two areas. First, easy gain tunable PID position controller without speed control loop is designed in order to construct feasible high performance drive system. Second, a simple but powerful zero phase error tracking strategy using the pre-designed function of the main control loop is presented for minimal tracking error in all operating conditions. Experimental results with a s-curve based position pattern commonly used in industrial field demonstrate the feasibility and effective performance of the approach.

• 전력전자학회논문지
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• 제9권5호
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• pp.430-437
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• 2004

본 논문에서는 고주파 스위칭 시 스위칭 손실의 감소, 구현의 용이성 및 인버터 제어를 위하여 요구되는 연산시간 감소 등 다양한 장점을 가진 4-Switch 인버터를 대상으로, 새로운 2상 스위칭 패턴(Pattern)과 이에 적용된 새로운 SRP-PWM(Separately Random Pulse Position PWM)기법을 제안한다. 본 논문에서는 고속운전 영역에서의 인버터 출력전류의 고조파 스펙트럼을 넓은 주파수 영역으로 즉, 특정주파수의 side-band로 고루 분산시키는 결과로부터 제안한 스위칭 패턴과 이에 적용된 새로운 SRP-PWM기법의 고조파 저감효과를 확인하고자 한다. 따라서 DSP를 이용한 IGBT인버터에 의한 실험을 수행하고, 이로부터 얻은 결과를 MATLAB/SIMULINK를 이용한 시뮬레이션 결과와 비교ㆍ분석하여 제안된 기법의 타당성을 검증하고자 한다.

• 한국산학기술학회논문지
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• 제11권7호
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• pp.2570-2578
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• 2010

본 논문에서는 임계전류도통모드로 동작하는 디지털제어 단상 역률개선(PFC; power-factor correction) 컨버터를 제안한다. 제안한 컨버터는 PFC를 위하여 DC-DC 부스트 컨버터 구조를 이용하며 인덕터전류를 임계도통모드로 동작시킨다. 또한 제안한 컨버터는 마이컴을 이용하여 디지털적으로 제어되기 때문에 제어회로는 간단해지고 컨버터는 더욱 효과적으로 동작한다. 본 논문에서는 먼저 제안한 컨버터의 동작원리를 설명하고 회로를 해석한다. 그리고 본 논문은 제안한 컨버터의 구현방법을 소프트웨어와 회로설계 부분으로 구분하여 구체적인 설계예와 함께 설명한다. 또한 설계된 회로파라미터에 의한 프로토타입 컨버터의 실험결과로 제안한 컨버터가 단상 PFC 컨버터로써 좋은 동작 특성을 가지고 있음을 보인다.

• Journal of Power Electronics
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• 제17권3호
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• pp.704-715
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• 2017

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.