• The Proceedings of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.9 no.5
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• pp.57-63
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• 1995

In this paper, 3-Phase PWM AC/DC step up type converter that reduces the harmonics and reactive power of the distribution line is analyzed and the stable control method is proposed as controlling the sinusoidal phase current and phase voltage in phase. In implementation of controller, simple control algorithm is derived as the instantaneous voltage control methods without current sensor. The instantaneous voltage is controled by PWM method and the switching frequency is presented in low range 3 [kHz] for reducing the switching loss. In case of active load, four quadrants operation converter regenerate power from the load to the power source is conducted. Through the computer simulation and experimentation, the proposed control method is justified.

• Journal of Korea Society of Industrial Information Systems
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• v.21 no.4
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• pp.21-30
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• 2016

In a single-phase power factor correction (PFC), the standard cascaded control algorithm using a proportional-integral-derivative (PID) controller has two main drawbacks: an inability to track sinusoidal current reference and low harmonic compensation capability. These drawbacks cause poor power factor and high harmonics in grid current. To improve these drawbacks, this paper uses a proportional-integral-derivative-resonant (PIDR) controller which combines a type-III PID with proportional-resonant (PR) controllers in the PFC. Based on a small signal model of the PFC, the type-III PID controller was implemented taking into account the bandwidth and phase margin of the PFC system. To adopt the PR controllers, the spectrum of inductor current of the PFC was analyzed in frequency domain. The hybrid PIDR controller were simulated using PSCAD/EMTDC and implemented on a 3 kW PFC prototype hardware. The performance results of the hybrid PIDR controller were compared with those of an individual type-III PID controller. Both controllers were implemented successfully in the single-phase PFC. The total harmonic distortion of the proposed controller were much better than those of the individual type-III PID controller.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.6
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• pp.558-565
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• 2015

Gallium nitride high-electron mobility transistor (GaN HEMT) is the strongest candidate for replacing Si MOSFET. Comparing the figure of merit (FOM) of GaN with the state-of-the-art super junction Si MOSFET, the FOM is much better because of the wide band gap characteristics and the heterojunction structure. Although GaN HEMT has many benefits for the power conversion system, the performance of the power conversion system with the GaN HEMT is sensitive because of its low threshold voltage ($V_{th}$) and even lower parasitic capacitance. This study examines the characteristics of a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT. The problem of unoptimized dead time is analyzed on the basis of the output capacitance of GaN HEMT. In addition, the printed circuit board (PCB) layout consideration is analyzed to reduce the negative effects of parasitic inductance. A comparison of the experimental results is provided to validate the dead time and PCB layout analysis for a phase-shifted full-bridge dc-dc converter with cascode GaN HEMT.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.3
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• pp.342-348
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• 2015

This paper presents a 1.9-GHz digital ${{\Delta}{\Sigma}}$ fractional-N PLL with a finite impulse response (FIR) filter embedded for noise suppression. The proposed digital implementation of FIR provides a simple method of increasing the number of taps without complicated calculation for gain matching. This work demonstrates 32 tap FIR filtering for the first time and successfully filtered the in-band phase noise generated from delta-sigma modulator (DSM). Design considerations are also addressed to find the optimum number of taps when the resolution of time-to-digital converter (TDC) is given. The PLL, fabricated in $0.11-{\mu}m$ CMOS, achieves a well-regulated in-band phase noise of less than -100 dBc/Hz for the entire range inside the bandwidth of 3 MHz. Compared with the conventional dual-modulus division, the proposed PLL shows an overall noise suppression of about 15dB both at in-band and out-of-band region.

• Journal of IKEEE
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• v.21 no.3
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• pp.240-243
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• 2017

CAN (controller area network) suffers from data bottleneck since the number of in-vehicle electronic modules significantly increases. To mitigate this problem, CAN-FD (CAN with flexible data rate) has been proposed. Transmission speed is same with CAN in arbitration phase but much higher than CAN in data phase, which successfully achieves both compatibility and efficiency. In this paper, a CAN-FD controller was designed in Verilog HDL and it was implemented and verified in FPGA. The designed controller can perform CAN-FD version 1.0 and CAN version 2.0A, 2.0B. Synthesized in 0.18um technology, its size is about 46,300 gates.

• Journal of Electrical Engineering and Technology
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• v.13 no.5
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• pp.1986-1995
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• 2018

In this paper, a novel neutral-point voltage balancing scheme for NPC three-level inverters using carrier-based sinusoidal pulse width modulation (SPWM) method is developed. The new modulation approach, based on the obtained expressions of zero sequence voltage in all six sectors, can significantly suppress the low-frequency voltage oscillation in the neutral point at high modulation index and achieve a fast voltage-balancing dynamic performance. The implementation of the proposed method is very simple. Another attractive feature is that the scheme can stably control any voltage difference between the two dc-link capacitors within a certain range without using any extra hardware. Furthermore, the presented scheme is also applicable to the single-phase NPC three-level inverter. It can maintain the neutral-point voltage balance at full modulation index and improve the voltage-balancing dynamic performance of the single-phase NPC three-level inverter. The performance of the proposed strategy and its benefits over other previous techniques are verified experimentally.

• Journal of Power Electronics
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• v.9 no.1
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• pp.74-84
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• 2009

The design and implementation of a high performance PID (Proportional Integral & Differential) style controller with zero-phase error tracking property is considered in this article. Unlike a ball screw driven system, the controller in a direct drive system should provide a high level of tracking performance while avoiding the problems due to the absence of the gear system. The stiff mechanical element in a direct drive system allows high precise positioning capability, but relatively high tracking ability with minimal position error is required. In this work, a feasible position controller named 'Unified PID controller' is presented. It will be shown that the function of the closed position loop can be designed into unity gain system in continuous time domain to provide minimal position error. The focus of this work is in two areas. First, easy gain tunable PID position controller without speed control loop is designed in order to construct feasible high performance drive system. Second, a simple but powerful zero phase error tracking strategy using the pre-designed function of the main control loop is presented for minimal tracking error in all operating conditions. Experimental results with a s-curve based position pattern commonly used in industrial field demonstrate the feasibility and effective performance of the approach.

• The Transactions of the Korean Institute of Power Electronics
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• v.9 no.5
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• pp.430-437
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• 2004

This thesis proposes novel SRP-PWM(Separately Random Pulse Position PWM) techniques and novel two-phase switching pattern applied to four-switch inverter, having various advantages such as operation time decrease that is required for decrease of switching damage, easy of implementation and inverter control at high frequency switching. In this thesis, we wish to confirm that SRP-PWM techniques disperse harmonic spectrum of inverter output current evenly into wide frequency area, that is, side-band of specification frequency. And we confirm the harmonic reduction effect of proposed techniques. Therefore, we will achieve an experiment by IGBT inverter using DSP and will verify the validity of proposed techniques compared with simulation results that use MATLAB/SIMULINK.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.11 no.7
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• pp.2570-2578
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• 2010

This paper presents a digital-controlled single-phase power-factor correction (PFC) converter operating in critical current conduction mode. The proposed converter utilizes the DC-DC boost converter topology for the PFC and operates the inductor current in critical conduction mode. Because the proposed converter is controlled digitally using a micom, its control circuit is simplified and the converter operates more effectively. This paper first explains the operational principles of the proposed converter and then analyzes the converter circuit. And this paper explains the implementation method of proposed converter with a detail design example, which is divided into software and circuit design parts. Also, it is shown through the experimental results of the prototype converter by the designed circuit parameters that the proposed converter has good performance as a single-phase PFC converter.

• Journal of Power Electronics
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• v.17 no.3
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• pp.704-715
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• 2017

For three-phase synchronization applications, the synchronous reference frame phase-locked loop (SRF-PLL) is probably the most widely used technique due to its ease of implementation and satisfactory phase tracking performance under ideal grid conditions. However, under unbalanced and distorted grid conditions, its performance tends to worsen. To deal with this problem, a variety of filtering stages have been proposed and used in SRF-PLLs for the rejection of disturbance components at the cost of degrading the dynamic performance. In this paper, to improve dynamic performance without compromising the filtering capability, an effective hybrid filtering stage is proposed and incorporated into the inner loop of a quasi-type-1 PLL (QT1-PLL). The proposed filtering stage is a combination of a moving average filter (MAF) and a modified delay signal cancellation (DSC) operator in cascade. The time delay caused by the proposed filtering stage is smaller than that in the conventional MAF-based and DSC-based PLLs. A small-signal model of the proposed PLL is derived. The stability is analyzed and parameters design guidelines are given. The effectiveness of the proposed PLL is confirmed through experimental results.