• Proceedings of the KWS Conference
• /
• 2003.05a
• /
• pp.210-212
• /
• 2003

Finite element analysis of welding processes, which entail phase evolution, heat transfer and deformation, is considered in this paper. Attention focuses on numerical implementation of the thermo-elastic-plastic constitutive equation proposed by Leblond et al in consideration of the transformation plasticity. Based upon the multiplicative decomposition of deformation gradient, hyperelastic formulation is employed for efficient numerical integration, and the algorithmic consistent moduli for elastic-plastic deformations including transformation plasticity are obtained in the closed form. The convergence behavior of the present implementation is demonstrated via a couple of numerical example.

• Proceedings of the Acoustical Society of Korea Conference
• /
• 1991.06a
• /
• pp.129-132
• /
• 1991

In this paper, the active noise controll system in duct is analyzed with real time implementation. The primary noise signal detected by microphone is modeled using adaptive algorithm and the secondary signal which has the same amplitude and 180$^{\circ}$phase shift with the primary noise signal is generated in the controller. We used the DSP56001 as a real-time processor and LMS algorithm as a adaptive technique, the experimental results shows that our system can reduce the noise level in duce to 15~40[db].

• Proceedings of the KIPE Conference
• /
• 2005.07a
• /
• pp.189-191
• /
• 2005

This paper proposes an implementation of a line- voltage sensorless three-phase active power filter. The line synchronization for an active power filter does not require any additional hardware. It can be properly operated under various line-voltage variation. Current compensation is done in the time domain allowing fast time response. All control functions are implemented in software using a single-chip microcontroller, thus simplifying the control circuit. It is shown via experimental results that the proposed controller gives good performance for the line-voltage sensorless active power filter.

• Journal of Technology Innovation
• /
• v.2 no.1
• /
• pp.116-141
• /
• 1994

This paper presents a model for R&D project selection and evaluation system design developed through literature review. The model emphasizes the fitness between the five elements of the system : evaluation phase and purpose, personnel and organization, evaluation critiria and decision model, evaluation form and procedure, and projects. The model was applied in real situation as a test case. The important findings are that a good project selection and evaluation model contributes only partially to the effectiveness of the project selection and that system development and implementation activity is a dynamic and multi-facetted learning process.

• Journal of Power Electronics
• /
• v.18 no.5
• /
• pp.1523-1535
• /
• 2018

High-performance Phase-Locked Loops (PLLs) are critical for grid synchronization in grid-tied power electronic applications. In this paper, a new single-phase All Digital Phase-Locked Loop (ADPLL) is proposed. It features fast transient response and good robustness under distorted grid conditions. It is designed for Field Programmable Gate Array (FPGA) implementation. As a result, a high sampling frequency of 1MHz can be obtained. In addition, a new OSG is adopted to track the power frequency, improve the harmonic rejection and remove the dc offset. Unlike previous methods, it avoids extra feedback loop, which results in an enlarged system bandwidth, enhanced stability and improved dynamic performance. In this case, a new parameter optimization method with consideration of loop delay is employed to achieve a fast dynamic response and guarantee accuracy. The Phase Detector (PD) and Voltage Controlled Oscillator (VCO) are realized by a Coordinate Rotation Digital Computer (CORDIC) algorithm and a Direct Digital Synthesis (DDS) block, respectively. The whole PLL system is finally produced on a FPGA. A theoretical analysis and experiments under various distorted grid conditions, including voltage sag, phase jump, frequency step, harmonics distortion, dc offset and combined disturbances, are also presented to verify the fast dynamic response and good robustness of the ADPLL.

• 한국정보통신설비학회:학술대회논문집
• /
• 2008.08a
• /
• pp.441-446
• /
• 2008

In this papers, a PLDRO(Phase Locked Dielectric Resonator Oscillator) is designed and implemented at the oscillator in which fundamental frequency is 18.3 GHz. The proposed PLDRO so as to improve the PLDRO of the general structure is designed to the goal of the minimize of the size and the performance improvement. Three VCO(Voltage controlled Oscillator) and the power combiner improved the output power. A VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is manufactured using a varactor diode to tune oscillating frequency electrically, and its phase is locked to reference frequency by SPD(Sampling Phase Detector). This product is fabricated on Teflon substrate with dielectric constant 2.2 and device is ATF -13786 of Ka-band using. This PLDRO generates an output power of 5.67 dBm at 18.3 GHz and has the characteristics of a phase noise of -80.10 dBc/Hz at 1 kHz offset frequency from carrier, the second harmonic suppression of -33 dBc. The proposed PLDRO can be used in Ka-band satellite applications

• Journal of Power Electronics
• /
• v.19 no.6
• /
• pp.1429-1439
• /
• 2019

Buck-Boost LLC (BBLLC) converters based on a PWM + phase control strategy are good candidates for high efficiency, high power density and wide input range applications. Nevertheless, they suffer from large computational complexity when it comes to calculating the optimal phase for ZVS of all the switches. In this paper, a method is proposed for a microcontroller unit (MCU) to calculate the optimal phase quickly and accurately. Firstly, a 2-D lookup table of the phase is established with an index of the input voltage and output current. Then, a bilinear interpolation method is applied to improve the accuracy. Meanwhile, simplification of the phase equation is presented to reduce the computational complexity. When compared with conventional curve-fitting and LUT methods, the proposed method makes the best tradeoff among the accuracy of the optimal phase, the computation time and the memory consumption of the MCU. Finally, A 350V-420V input, 24V/30A output experimental prototype is built to verify the proposed method. The efficiency can be improved by 1% when compared with the LUT method, and the computation time can be reduced by 13.5% when compared with the curve-fitting method.

• Journal of the Korean Institute of Telematics and Electronics B
• /
• v.29B no.2
• /
• pp.9-17
• /
• 1992

In recent years, object-orientation is rising to notice as a new paradigm for developing software. This paper suggests the diagramming technique and a tool for developing C++ program effectively. This technique can represent the modularity and the interactions of classes definitely by emphasizing the characteristics of classes of C++. It can do the direct mapping from the logical idea to the physical screen image, so programmers can reuse the design resources in design phase as well as transforming the resources into chode in the implementation phase.

• Journal of electromagnetic engineering and science
• /
• v.5 no.1
• /
• pp.1-7
• /
• 2005

The implementation of a simple analog in-phase combiner is presented for a high capacity radio relay system with space diversity. It provides good performance in terms of simple hardware and easy control, and measured results are in good agreement with simulated ones. To suggest practical applications, signatures with/without diversity are measured for STM-1 signal of 64-QAM radio relay system combined with a 13-tap equalizer, and they provided more than 25 dB fade depth at 10$^{-3}$ BER under the frequency selective fading condition.

• Proceedings of the KIEE Conference
• /
• 1987.07b
• /
• pp.950-953
• /
• 1987

A wave difference method(WDH) phase detector for timing recovery is designed in the digital subscriber loop receiver. This paper describes the architecture and experimental results of the WDM, tankless timing extraction PLL. The results show that the designed WDM timing extraction circuit have stable jitter performance without the use of high precision LC tank circuit.