• IE interfaces
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• v.13 no.3
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• pp.539-547
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• 2000

An architecture of a Web-based Decision Support system for mathematical analysis is presented. Front-end modules provide web-client GUI environment for mathematical analysis. The networking architecture is built upon client/server system by Java socket and accesses database by JDBC in WWW. Back-end modules provide decision supporting service and data management for mathematical programming analysis. In the back-end any analysis tools, such as mathematical optimizer, simulation package, or statistics package can be used. As an application example for this implementation, optimal facility replacement decision problem is selected. In the implementation the optimal facility replacement decision problem is formulated as a shortest path problem. It uses Oracle DB and CPLEX package as the mathematical optimizer. While ORAWeb is designed and implemented on the optimal facility replacement problem, it can easily be extended to any decision supporting problems that would require mathematical optimization process.

• Structural Engineering and Mechanics
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• v.52 no.4
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• pp.739-753
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• 2014

There have been many packages that can be employed to analyze plane frames. However, because most structural analysis packages suffer from closeness of system, it is very difficult to integrate it with an optimization package. To overcome the difficulty, we proposed a possible alternative, DAMDO, which integrate Design, Analysis, Modeling, Definition, and Optimization phases into an integrative environment. The DAMDO methodology employs neural networks to integrate structural analysis package and optimization package so as not to need directly to integrate these two packages. The key problem of the DAMDO approach is how to generate a set of reasonable random designs in the first phase. According to the characteristics of optimized plane frames, we proposed the ratio variable approach to generate them. The empirical results show that the ratio variable approach can greatly improve the accuracy of the neural networks, and the plane frame optimization problems can be solved by the DAMDO methodology.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2003.09a
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• pp.165-172
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• 2003

Wafer-level packaging technology has become established with increase of demands for miniaturizing and realizing lightweight electronic devices evolution. This packaging technology enables the smallest footprint of packaged chip. Various structures and processes has been proposed and manufactured currently, and products taking advantages of wafer-level package come onto the market. The package enables mounting semiconductor chip on print circuit board as is a case with conventional die-level CSP's with BGA solder bumps. Bumping technology is also advancing in both lead-free solder alternative and wafer-level processing such as stencil printing using solder paste. It is known lead-free solder bump formation by stencil printing process tend to form voids in the re-flowed bump. From the result of FEM analysis, it has been found that the strain in solder joints with voids are not always larger than those of without voids. In this paper, characteristics of wafer-level package and effect of void in solder bump on its reliability will be discussed.

• Proceedings of the KIEE Conference
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• 1993.07b
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• pp.1286-1288
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• 1993

An analytical method for the optimum design of the minimum die size in power MOSFETs is presented. The proposed methodology considers the thermal resistance of the package and gives the minimum die area for desired drain current levels. The results are compared with experimental data and it is found that the die size mar be reduced if it is designed according to the proposed design procedure.

• Fashion & Textile Research Journal
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• v.25 no.3
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• pp.333-345
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• 2023

The rising demand for fashion do-it-yourself (DIY) products that cater to individual preferences and which allow for creative expression has highlighted the need for systematic organization within the clothing society. This study addresses this gap by identifying and discussing clothing DIY packages and proposes a systematic package model comprising essential raw materials, commercial patterns, and production instructions. Four key elements have been emphasized to differentiate and enhance the product. Firstly, highly practical commercial patterns have been developed to facilitate easy transformations - from blouses to dresses. Furthermore, the versatility of these patterns has been optimized so as to allow their utilization as outerwear, increasing their efficiency. Secondly, to accommodate diverse body shapes, the package offers six different sizes, providing users with a range of options tailored to their specific measurements. Thirdly, detailed production instructions are provided, supplemented by a Q&A bulletin board. The instructions are available in a printed format, featuring actual photographs on A4 paper, while video production instructions are accessible via a QR code, ensuring comprehensive guidance. Lastly, the basic package comprises clothing patterns, production instructions, fabrics, and labels, providing a complete toolkit for clothing DIY enthusiasts. This study aims to contribute to the development of the hobby sewing field and to establish a practical resource for the clothing DIY package industry.

• JSTS:Journal of Semiconductor Technology and Science
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• v.1 no.4
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• pp.216-231
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• 2001

Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.13-22
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• 2004

In MEMS devices, packaging induced stress or stress induced structure deformation become increasing concerns since it directly affects the performance of the device. In this paper, deformation behavior of MEMS gyroscope package subjected to temperature change is investigated using high-sensitivity moire interferometry. Using the real-time moire setup, fringe patterns are recorded and analyzed at several temperatures. Temperature dependent analyses of warpages and extensions/contractions of the package are presented. Linear elastic behavior is documented in the temperature region of room temperature to $125^{\circ}C$. Analysis of the package reveals that global bending occurs due to the mismatch of thermal expansion coefficient between the chip, the molding compound and the PCB. Detailed global and local deformations of the package by temperature change are investigated, concerning the variation of natural frequency of MEMS gyro chip.

• 제어로봇시스템학회:학술대회논문집
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• 1986.10a
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• pp.337-340
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• 1986

A software package CARDS for general purpose robot design, control, and simulation has been developed and is presented here. CARDS (Computer Aided Robot Design and Simulation) consists of a collection of standardized subroutine modules that carry out typical kineamatic, dynamic, and control computations so that the user only needs to write a main program that further defines a particular robot configuration and the task to be performed. It provides users a complete simulation environment, so that it will be a valuable engineering tool for mechanical designers as well as electric control designers.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.39-44
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• 2008

In this paper, fully embedded 2.4GHz WLAN band pass filter (BPF) was investigated into a multi-layered organic packaging substrate using high Q spiral stacked inductors and high Dk MIM capacitors for low cost RF System on Package (SOP) applications. The proposed 2.4GHz WLAN BPF was designed by modifying chebyshev second order filter circuit topology. It was comprised of two parallel LC resonators for obtaining two transmission zeros. It was designed by using 2D circuit and 3D EM simulators for finding out optimal geometries and verifying their applicability. It exhibited an insertion loss of max -1.7dB and return loss of min -l7dB. The two transmission zeros were observed at 1.85 and 6.7GHz, respectively. In the low frequency band of $1.8GHz{\sim}1.9GHz$, the stop band suppression of min -23dB was achieved. In the high frequency band of $4.1GHz{\sim}5.4GHz$, the stop band suppression of min -l8dB was obtained. It was the first embedded and the smallest one of the filters formed into the organic packaging substrate. It has a size of $2.2{\times}1.8{\times}0.77mm^3$.

• Journal of Welding and Joining
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• v.22 no.6
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• pp.36-42
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• 2004

Experimental and numerical approaches on the thermal fatigue for the solder joint of flip chip package are discussed. However, it is one of the most difficult problems to choose the proper fatigue model. It was found that viscoplstic FE model with Darveaux method was very desirable and useful to predict the thermal fatigue life of solder joint for flip chip package under $208{\~}423K$ thermal cycling condition such as steep slope of temperature(JEDEC standard condition C). Thermal fatigue life was 1075 cycles as a result of viscoplatic model. It was a good agreement compared to the experimental. And also, it was found from the experimental that probability of the thermal fatigue life was $60{\%}$ at 1500 cycles.