• 대한전자공학회논문지SD
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• 제44권10호
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• pp.33-37
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• 2007

본 논문에서는 vertical shunt symmetric inductor를 이용하여 CMOS LNA의 설계에 있어서 회로의 면적을 줄이는 설계기술 및 구현에 관한 내용을 제시하고자 한다. 본 연구에 있어서 vertical shunt symmetric inductor는 LNA의 입력단과 출력단을 3GHz로 정합하기 위해서 사용되었다. 이렇게 구현된 보다 면적에 있어서 효율적인 증폭기를 0.18um digital logic공정으로 구현되었다. 본 논문에서는 일반적으로 LNA에서 사용하고 있는 inductor를 이용하는 경우와, vertical shunt symmetric inductor를 이용하여 LNA를 설계하는 경우에 대한 부분을 비교하였고, 최종적으로 면적에 효율적인 회로설계 기술을 제시하고자 한다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2022년도 춘계학술발표대회
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• pp.161-164
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• 2022

Homomorphic Encryption (HE) schemes have been recently growing as a reliable solution to preserve users' information owe to maintaining and operating the user data in the encrypted state. In addition to that, several Neural Networks models merged with HE schemes have been developed as a prospective tool for privacy-preserving machine learning. Those mentioned works demonstrated that it is possible to match the accuracy of non-encrypted models but there is always a trade-off in the computation time. In this work, we evaluate the implementation of CKKS HE scheme operations over the layers of a LeNet5 convolutional inference model, however, owing to the limitations of the evaluation environment, the scope of this work is not to develop a complete LeNet5 encrypted model. The evaluation was performed using the MNIST dataset with Microsoft SEAL (MSEAL) open-source homomorphic encryption library ported version on Python (PyFhel). The behavior of the encrypted model, the limitations faced and a small description of related and future work is also provided.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2020년도 춘계학술발표대회
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• pp.272-274
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• 2020

최근 컴퓨터 프로그램의 크기가 증가하고 목적이 다양해지면서 프로그램의 취약점에 대한 위험이 증가하고 있다. 공격자 보다 먼저 프로그램 취약점을 찾아내기 위한 여러 기법들이 있다. 그 중 프로그램의 취약점을 보다 효율적으로 찾아내기 위한 기법 중 하나인 퍼징 (Fuzzing) 은 프로그램에 무작위로 입력 데이터를 입력하여 프로그램의 정의되지 않은 영역을 검증하는 기법이다. 이러한 입력 데이터를 최대한 적은 시간과 자원을 소모하여 생성하기 위해 인공지능과 퍼징을 결합하는 연구가 활발히 진행 중이다. 본 논문에서는 퍼징의 개념 및 종류에 대해 설명하고 퍼징과 인공지능이 결합된 최신 연구에 대해 서술한다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2020년도 춘계학술발표대회
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• pp.260-263
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• 2020

현재 전 세계 수많은 모바일 기기들은 보안에 민감한 애플리케이션들과 운영체제 요소들을 보호하기 위하여 ARM TrustZone 기반 신뢰실행환경 (Trusted Execution Environment) 을 사용한다. 하지만, 신뢰실행환경이 제공하는 높은 보안성에도 불구하고, 이에 대한 성공적인 공격 사례들이 지속적으로 확인되고 있다. 본 논문에서는 이러한 공격들을 가능하게 하는 ARM TrustZone 기반 신뢰실행환경의 취약점들을 소개한다. 이와 더불어 취약점들을 보완하기 위한 다양한 방어 기법 연구에 대해 살펴본다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2020년도 춘계학술발표대회
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• pp.264-267
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• 2020

클라우드가 보편적으로 활용되면서 클라우드 서버에 정보를 저장하거나 연산을 하는 일은 일상이 되었다. 그러나, 이러한 클라우드 컴퓨팅 서비스가 급격히 증가하면서, 개인정보보호와 데이터 보안성, 기밀성 및 시스템의 안정성에 대한 우려가 높아지고 있다. 클라우드는 데이터를 위탁받아 연산하는 과정에서 사용자들의 개인정보를 유출시킬 수 있는 문제점이 있다. 이러한 문제점을 해결하기 위한 방법 중 현재 가장 각광 받고 있는 해결책은 바로 동형암호기술이다. 동형암호는 이전 암호체계와 다르게 사용자의 암호화된 데이터를 복호화하지 않고서도 연산할 수 있어서, 이를 이용하게 되면 사용자 데이터의 기밀성을 보장하면서도 원하는 결과를 얻을 수 있다. 그러나, 동형암호를 클라우드 컴퓨팅 환경에 적용하는데 가장 큰 장애물은 바로 연산 오버헤드가 대단히 크다는 점이다. 본 연구에서는 최신 동형암호 기술을 소개하고 연산속도를 증가시키기 위한 솔루션들에 대해 알아보고자 한다.

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2023년도 춘계학술발표대회
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• pp.123-125
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• 2023

As deep learning has become an essential part of human lives, the requirement for Deep Learning as a Service (DLaaS) is growing. Since using remote cloud servers induces privacy concerns for users, a Fully Homomorphic Encryption (FHE) arises to protect users' sensitive data from a malicious attack in the cloud environment. However, the FHE cannot support several computations, including the most popular activation function, Rectified Linear Unit (ReLU). This paper analyzes several polynomial approximation methods for ReLU to utilize FHE in DLaaS.

• JSTS:Journal of Semiconductor Technology and Science
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• 제17권2호
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• pp.167-173
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• 2017

In this paper, the characterization of the vertical position of trapped charges in the charge-trap flash (CTF) memory is performed in the novel CTF memory cell with gate-all-around structure using technology computer-aided design (TCAD) simulation. In the CTF memories, injected charges are not stored in the conductive poly-crystalline silicon layer in the trapping layer such as silicon nitride. Thus, a reliable technique for exactly locating the trapped charges is required for making up an accurate macro-models for CTF memory cells. When a programming operation is performed initially, the injected charges are trapped near the interface between tunneling oxide and trapping nitride layers. However, as the program voltage gets higher and a larger threshold voltage shift is resulted, additional charges are trapped near the blocking oxide interface. Intrinsic properties of nitride including trap density and effective capture cross-sectional area substantially affect the position of charge centroid. By exactly locating the charge centroid from the charge distribution in programmed cells under various operation conditions, the relation between charge centroid and program operation condition is closely investigated.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권3호
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• pp.360-369
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• 2012

The causes of showing different subthreshold slopes (SS) in programmed and erased states for two different charge trap flash (CTF) memory devices, SONOS type flash memory with gate-all-around (GAA) structure and TANOS type NAND flash memory with planar structure were investigated. To analyze the difference in SSs, TCAD simulation and low-frequency noise (LFN) measurement were fulfilled. The device simulation was performed to compare SSs considering the gate electric field effect to the channel and to check the localized trapped charge distribution effect in nitride layer while the comparison of noise power spectrum was carried out to inspect the generation of interface traps ($N_{IT}$). When each cell in the measured two memory devices is erased, the normalized LFN power is increased by one order of magnitude, which is attributed to the generation of $N_{IT}$ originated by the movement of hydrogen species ($h^*$) from the interface. As a result, the SS is degraded for the GAA SONOS memory device when erased where the $N_{IT}$ generation is a prominent factor. However, the TANOS memory cell is relatively immune to the SS degradation effect induced by the generated $N_{IT}$.

• Journal of Korean Vacuum Science & Technology
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• 제4권3호
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• pp.73-77
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• 2000

Single crystal and polycrystalline Si thin films were doped with phosphorus by a 2-zone diffusion method to develop the low-resistivity polycrystalline Si electrode for a hemispherical grain. Solid phosphorus source was used in order to achieve uniformly and highly doped surface region of polycrystalline Si films having rough surface morphology. In case of 2-zone diffusion method, it is proved that the heavy doping near the surface area can be achieved even at a relatively low temperature. SIMS analysis revealed that phosphorus doping concentration in case of using solid P as a doping source was about 50 times as that of phosphine source at 750$^{\circ}C$. Also, ASR analysis revealed that the carrier concentration was about 50 times as that of phosphine. In order to evaluate the electrical characteristics of doped polycrystalline Si films for semiconductor devices, MOS capacitors were fabricated to measure capacitance of polycrystalline Si films. In ${\pm}$2 V measuring condition, Si films, doped with solid source, have 8% higher $C_{min}$ than that of unadditional doped Si films and 3% higher $C_{min}$ than that of Si films doped with $PH_3$ source. The leakage current of these films was a few fA/${\mu}m^2$. As a result, a 2-zone diffusion method is suggested as an effective method to achieve highly doped polycrystalline Si films even at low temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권2호
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• pp.204-209
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• 2016

The analyses on self-heating effect in 7 nm node non-rectangular Bulk FinFET device were performed using 3D device simulation with consideration to contact via and pad. From self-heating effect simulation, the position where the maximum lattice temperature occurs in Bulk FinFET device was investigated. Through the comparison of thermal resistance at each node, main heat transfer path in Bulk FinFET device can be determined. Self-heating effect with device parameter and operation temperature was also analyzed and compared. In addition, the impact of interconnects which are connected between the device on self-heating effect was investigated.