• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.7
• /
• pp.1608-1616
• /
• 2015

This paper describes an efficient hardware implementation of lightweight encryption algorithm LEA-128/192/256 which supports for three master key lengths of 128/192/256-bit. To achieve area-efficient and low-power implementation of LEA crypto- processor, the key scheduler block is optimized to share hardware resources for encryption/decryption key scheduling of three master key lengths. In addition, a parallel register structure and novel operating scheme for key scheduler is devised to reduce clock cycles required for key scheduling, which results in an increase of encryption/decryption speed by 20~30%. The designed LEA crypto-processor has been verified by FPGA implementation. The estimated performances according to master key lengths of 128/192/256-bit are 181/162/109 Mbps, respectively, at 113 MHz clock frequency.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2015.10a
• /
• pp.227-229
• /
• 2015

모든 사물에 인터넷이 연결되는 사물 인터넷(IoT: Internet of Things)시대가 열렸다. IoT 디바이스들을 연결하기 위해 클라우드 또한 더욱 관심이 높아지고 있다. IoT 디바이스를 연결한 클라우드는 작은 단위의 작업들을 다량으로 수행하게 된다. IoT 서비스에서 발생하는 작업들을 효율적으로 처리하기 위해서는 적합한 작업 스케줄링이 반드시 필요하다. 본 논문에서는 오픈소스 기반의 플랫폼인 오픈스택(OpenStack)에서 Filter 스케줄러와 Chance 스케줄러를 VM 개수에 따라 단위 시간동안 성능을 비교 분석한다. 이를 통해 오픈스택에서 IoT 서비스 사용자들을 위해 합리적인 스케줄러 방법을 도출해낼 수 있다

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.42 no.5 s.335
• /
• pp.63-72
• /
• 2005

This paper describes a new approach for the operating system level power management to reduce the energy consumed in the IO devices in a robot platform, which provides various functions such as navigation, multimedia application, and wireless communication. The policy proposed in the paper, which was named the Energy-Aware Job Schedule (EAJS), rearranges the jobs scattered so that the idle periods of the devices are clustered into a time period and the devices are shut down during their idle period. The EAJS selects a schedule that consumes the minimum energyamong the schedules that satisfy the buffer and time constraints. Note that the burst job execution needs a larger memory buffer and causes a longer time delay from generating the job request until to finishing it. A prototype of the EAJS is implemented on the Linux kernel that manages the robot system. The experiment results show that a maximum $44\%$ power saving on a DSP and a wireless LAN card can be obtained with the EAJS.

• Journal of the Korea Society of Computer and Information
• /
• v.24 no.9
• /
• pp.1-8
• /
• 2019

In this paper, we propose a performance isolation of shared space for virtualized SSD based storage systems, to solve the weakness in a VSSD framework. The proposed scheme adopts a CFQ scheduler and a shared space-based FTL for the fairness and the performance isolation for multiple users on virtualized SSD based storage systems. Using the CFQ scheduler, we ensure SLOs for the storage systems such as a service time, a allocated space, and a IO latency for users on the virtualized storage systems. In addition, to improve a throughput and reduce a computational latency for garbage collection, a shared space-based FTL is adopted to maintain the information of SLOs for users and it manages shared spaces among the users. In our experiments, the proposal improved the throughput of garbage collection by 7.11%, on average, and reduced the computational latency for garbage collection by 9.63% on average, compared to the previous work.

• KSII Transactions on Internet and Information Systems (TIIS)
• /
• v.14 no.8
• /
• pp.3201-3223
• /
• 2020

Wireless communication has become the promising technology in the recent times because of its applications in Internet of Things( IoT) devices. The IEEE 802.15.4e has become the key technology for IoT devices which utilizes the Time-Slotted Channel Hopping (TSCH) networks for the communication between the devices. In this paper, we develop a Two Level Scheduling Algorithm (TLSA) for scheduling multiple packets with different arrival rate at the source nodes in a TSCH networks based on the link activated by a centralized scheduler. TLSA is developed by considering three types of links in a network such as link i with packets arrival type 1, link j with packets arrival type 2, link k with packets arrival type 3. For the data packets arrival, two stages in a network is considered.At the first stage, the packets are considered to be of higher priority.At the second stage, the packets are considered to be of lower priority.We introduce level 1 schedule for the packets at stage 1 and level 2 schedule for the packets at stage 2 respectively. Finally, the TLSA is validated with the two different energy functions i.e., y = e^ax - 1 and y = 0.5x² using MATLAB 2017a software for the computation of average and worst ratios of the two levels.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2014.10a
• /
• pp.285-287
• /
• 2014

This paper describes a design of area-efficient/low-power cryptographic processor for lightweight block cipher algorithm HIGHT which was approved as a cryptographic standard by KATS and ISO/IEC. The HIGHT algorithm which is suitable for the security of IoT(Internet of Things), encrypts a 64-bit plain text with a 128-bit cipher key to make a 64-bit cipher text, and vice versa. For area-efficient and low-power implementation, we adopt 32-bit data path and optimize round transform block and key scheduler to share hardware resources for encryption and decryption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2015.05a
• /
• pp.401-403
• /
• 2015

This paper describes an efficient hardware design of 128-bit block cipher algorithm LEA(lightweight encryption algorithm). In order to achieve area-efficient and low-power implementation, round block and key scheduler block are optimized to share hardware resources for encryption and decryption. The key scheduler register is modified to reduce clock cycles required for key scheduling, which results in improved encryption/decryption performance. FPGA synthesis results of the LEA processor show that it has 2,364 slices, and the estimated performance for the master key of 128/192/256-bit at 113 MHz clock frequency is about 181/162/109 Mbps, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
• /
• v.19 no.4
• /
• pp.888-894
• /
• 2015

This paper describes an efficient hardware design of Lightweight Encryption Algorithm (LEA) developed by National Security Research Institute(NSRI). The LEA crypto-processor supports for master key of 128-bit. To achieve small-area and low-power implementation, an efficient hardware sharing is employed, which shares hardware resources for encryption and decryption in round transformation block and key scheduler. The designed LEA crypto-processor was verified by FPGA implementation. The LEA core synthesized with Xilinx ISE has 1,498 slice elements, and the estimated throughput is 216.24 Mbps with 135.15 MHz.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.15 no.5
• /
• pp.570-576
• /
• 2015

Existing flash storage devices such as universal flash storage and solid state disk support command queuing to improve storage I/O bandwidth. Command queuing allows multiple read/write requests to be pending in a device queue. Because multi-channel and multi-way architecture of flash storage devices can handle multiple requests simultaneously, command queuing is an indispensable technique for utilizing parallel architecture. However, command queuing can be harmful to the latency of fsync system call, which is critical to application responsiveness. We propose a dynamic queue depth adaptation technique, which reduces the queue depth if user application is expected to send fsync calls. Experiments show that the proposed technique reduces the fsync latency by 79% on average compared to the original scheme.

• Proceedings of the Korea Information Processing Society Conference
• /
• 2019.05a
• /
• pp.60-61
• /
• 2019

Drones are opening new horizon as a major Internet-of-Things (IoT) player which is a network of objects. Drone needs to charge itself during providing services from the charging stations. If there are lots of drones and one charging station, then it is a critical situation to decide which drone should get charged first and make order of priorities for drones to get charged sequentially. In this paper, we propose an efficient scheduling algorithm for drone power charging (ESADPC), in which charging station would have a scheduler to decide which drone can get charged earlier among many other drones. Simulation results have showed that our algorithm reduces the deadline miss ration and turnaround time.