• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.4A
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• pp.324-329
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• 2009

In this paper, a novel Snowflake-shaped microstrip patch antenna for application in the WLAN(5.2/5.8GHz) band is designed and fabricated. The size of antenna is $21.2{\times}16mm^2$ and substrate is used Taconic-RF30. To obtain sufficient bandwidth in Return loss <-10dB and dual resonance characteristic, the Short-pin is inserted on the patch and the coaxial probe source is used. The measured results of fabricated antenna show 220MHz and 135MHz bandwidth in Return loss <-10dB referenced to the WLAN(5.2/5.8GHz) band. The measured antenna gain is $4.7{\sim}6.9dBi$ in the WLAN(5.2/5.8GHz) band. The experimental 3-dB beam width in I-plane and H-plane are $73.2^{\circ}/82.75^{\circ}$ for 5.1500Hz, $74.56^{\circ}/83.63^{\circ}$ for 5.3500Hz, and $86.24^{\circ}/85.15^{\circ}$ for 5.7850Hz, respectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.5 s.335
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• pp.55-62
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• 2005

In this paper, we propose an efficient symbol detection algorithm for space-frequency OFDM (SF-OFDM) transmit diversity scheme and present the implementation results of the SF-OFDM WLAN baseband processor with the proposed algorithm. When the number of sub-carriers in SF-OFDM scheme is small, the interference between adjacent sub-carriers may be generated. The proposed algorithm eliminates this interference in a parallel manner and obtains a considerable performance improvement over the conventional detection algorithm. The bit error rate (BER) performance of the proposed detection algorithm is evaluated by the simulation. In the case of 2 transmit and 2 receive antennas, at $BER=10^{-4}$ the proposed algorithm obtains about 3 dB gain over the conventional detection algorithm. The packet error rate (PER), link throughput, and coverage performance of the SF-OFDM WLAN with the proposed detection algorithm are also estimated. For the target throughput at $80\%$ of the peak data rate, the SF-OFDM WLAN achieves the average SNR gain of about 5.95 dB and the average coverage gain of 3.98 meter. The SF-OFDM WLAN baseband processor with the proposed algorithm was designed in a hardware description language and synthesized to gate-level circuits using 0.18um 1.8V CMOS standard cell library. With the division-free architecture, the total logic gate count for the processor is 945K. The real-time operation is verified and evaluated using a FPGA test system.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.6B
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• pp.595-604
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• 2009

The HCCA reserves the channel resources based on the mean data rate in IEEE 802.11e. It may cause either the waste of channel resource or the increase of transmission delay at MAC layer if the frame size is rapidly varied when a compressed mode video codec such as MPEG video is used. To solve these problems, it is developed that the packet scheduler allocates the wireless resource adaptation by according to the packet size. However, it is difficult to perform the admission control because of the difficulty with calculating the available resources. In this paper, we propose a CAC mechanism to solve the problem that may not satisfy the QoS by increasing traffic load in case of using EDCA. Especially, the proposed CAC mechanism calculates the EB of TSs using the traffic information transmitted by the application layer and the number of average transmission according to the wireless channel environment, and then determines the admission of the TS based on the EB. According to the simulation results of the proposed CAC mechanism, it admitted the TSs under the loads which are satisfied within the delay bound. Therefore, the proposed mechanism guarantees QoS of streaming services effectively.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.8
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• pp.623-631
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• 2013

Wireless LAN (WLAN) interface is one of the major sources drastically depleting the battery power of mobile devices such as smartphones and tablets. Most commercial mobile devices employ a power saving technique putting their WLAN interface into a sleep state when there is no network traffic, and thereby, save the battery power. However, since an access point (AP) just transmits the packet(s) received from a server to the corresponding mobile device immediately, it may cause a problem that the mobile device constantly remains in an awake state so that its battery power is rapidly drained. In this paper, we point out this problem and propose a new scheme that can save the mobile device's battery power with an adaptive packet scheduling at the AP side. From the experimental results based on a testbed, we found that the proposed scheme outperforms existing schemes over 50% in terms of power saving.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.2 no.4
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• pp.42-51
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• 2003

In this paper, we are going to analyze on relation of an output spectrum along phase distortion of power amplifier in wireless LAN system, and then considered an ACPR characteristic of power amplifier and consideration of an OFDM method for this. Also, we did implementation for OFDM modulation and transmission section of an IEEE 802.11a standard to have transmission speed of the maximum 54Mbps in order to know an OFDM modulation method and relation of non-linear characteristic of power amplifier. The non-linear characteristic of power amplifier did modeling with AM-to-AM and AM-to-PM, and we analyzed an output spectrum characteristic along phase distortion composed input signal supply for power amplifier. When output spectrum analysis results phase distortion increased, and an AM-to-PM characteristic of power amplifier in 5 degrees, the output spectrum was satisfied with a demand spectrum in P1 dB, but 10-20 degrees were able to confirm what cannot be satisfied with a demand spectrum in phase distortion. Also, an output spectrum of power amplifier by frequency re-growth generated by a non-linear characteristic of power amplifier did not satisfied in P1dE. therefore, a back-off value was requested according to an AM-to-PM distortion degree, and smaller back-off value were able to know what demand became in case of modulation section that used OFDM.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.372-375
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• 2008

IEEE 802.11e standardized the EDCA mechanism to support the priority based QoS. And the virtual collision handler schedules the transmission time of each MAC frame using the internal back-off window according to the access category(AC). This can provides the differentiated QoS to real-time services at the medium traffic load condition. However, the transmission delay of MAC frame for real-time services may be increased as the traffic load of best effort service increases. It becomes more critical when the real-time service uses a compressed mode video codec such as moving picture experts group(MPEG) 4 codec. That is because each frame has the different importance. That is, the I-frame has more information as compared with the P- and the B-frame. In this paper, we proposed a buffer management algorithm based on the frame importance and the delay bound. The proposed algorithm is consisted of the traffic regulator based on the dual token bucket algorithm and the active queue management algorithm. The traffic regulator reduces the transmission rate of lower AC until that the virtual collision handler can transmit an I-frame. And the active queue management discards frame based on the importance of each frame and the delay bound of head of line(HoL) frame when the channel resource is insufficient.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.726-732
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• 2019

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%.