• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.372-375
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• 2008

IEEE 802.11e standardized the EDCA mechanism to support the priority based QoS. And the virtual collision handler schedules the transmission time of each MAC frame using the internal back-off window according to the access category(AC). This can provides the differentiated QoS to real-time services at the medium traffic load condition. However, the transmission delay of MAC frame for real-time services may be increased as the traffic load of best effort service increases. It becomes more critical when the real-time service uses a compressed mode video codec such as moving picture experts group(MPEG) 4 codec. That is because each frame has the different importance. That is, the I-frame has more information as compared with the P- and the B-frame. In this paper, we proposed a buffer management algorithm based on the frame importance and the delay bound. The proposed algorithm is consisted of the traffic regulator based on the dual token bucket algorithm and the active queue management algorithm. The traffic regulator reduces the transmission rate of lower AC until that the virtual collision handler can transmit an I-frame. And the active queue management discards frame based on the importance of each frame and the delay bound of head of line(HoL) frame when the channel resource is insufficient.

• Journal of information and communication convergence engineering
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• v.8 no.3
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• pp.289-294
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• 2010

In the vehicle communication system, transferred information is needed to be detected as possible as fast in order to inform car status located in front and rear side. Through the moving vehicle information, we can avoid the crash caused by sudden break of front one or acquire to real time traffic data to check the detour road. To be connecting the wireless communication between the vehicles, fast timing synchronization can be a key factor. Finding out the sync point fast is able to have more marginal time to compensate the distorted signals caused by channel variance. Thus, we introduce the combination method which helps find out the start of frame quickly. It is executed by auto-correlation and cross-correlation simultaneously using only short preambles. With taking the absolute value at the implemented synch block output, the proposed method shows much better system performance to us.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• v.9 no.1
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• pp.578-582
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• 2005

This paper describes MAC schemes for QoS enhancement taking into account the traffic characteristics and network states over IEEE 802.11 wireless networks. Our approach uses AR as a Backoff parameter and to slide IFS adaptively for increasing the medium utilization ratio and throughput, and providing fairness. In addition, we evaluate through simulations using NS-2 the performance of proposed MAC scheme and compare it with other MAC schemes.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.2 no.4
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• pp.42-51
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• 2003

In this paper, we are going to analyze on relation of an output spectrum along phase distortion of power amplifier in wireless LAN system, and then considered an ACPR characteristic of power amplifier and consideration of an OFDM method for this. Also, we did implementation for OFDM modulation and transmission section of an IEEE 802.11a standard to have transmission speed of the maximum 54Mbps in order to know an OFDM modulation method and relation of non-linear characteristic of power amplifier. The non-linear characteristic of power amplifier did modeling with AM-to-AM and AM-to-PM, and we analyzed an output spectrum characteristic along phase distortion composed input signal supply for power amplifier. When output spectrum analysis results phase distortion increased, and an AM-to-PM characteristic of power amplifier in 5 degrees, the output spectrum was satisfied with a demand spectrum in P1 dB, but 10-20 degrees were able to confirm what cannot be satisfied with a demand spectrum in phase distortion. Also, an output spectrum of power amplifier by frequency re-growth generated by a non-linear characteristic of power amplifier did not satisfied in P1dE. therefore, a back-off value was requested according to an AM-to-PM distortion degree, and smaller back-off value were able to know what demand became in case of modulation section that used OFDM.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.4
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• pp.53-63
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• 2009

This work proposes a 10b 100MS/s 27.2mW $0.8mm^2$ 0.18um CMOS ADC for WLAN such as an IEEE 802.11n standard. The proposed ADC employs a three-stage pipeline architecture and minimizes power consumption and chip area by sharing as many circuits as possible. Two multiplying DACs share a single amplifier without MOS switches connected in series while the shared amplifier does not show a conventional memory effect. All three flash ADCs use only one resistor ladder while the second and third flash ADCs share all pre-amps to further reduce power consumption and chip area. The interpolation circuit employed in the flash ADCs halves the required number of pre-amps and an input-output isolated dynamic latch reduces the increased kickback noise caused by the pre-amp sharing. The prototype ADC implemented in a 0.18um n-well 1P6M CMOS process shows the DNL and INL within 0.83LSB and 1.52LSB at 10b, respectively. The ADC measures an SNDR of 52.1dB and an SFDR of 67.6dB at a sampling rate of 100MS/s. The ADC with an active die area of $0.8mm^2$ consumes 27.2mW at 1.8V and 100MS/s.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.10
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• pp.6604-6610
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• 2015

In this paper, an efficient Wireless Access in Vehicular Environment (WAVE) packet transmission scheme for railroad communication is proposed. WAVE communication is a wireless local area network (WLAN) based communication and it is developed to be suitable for vehicular communication. There has been a lot of study on WAVE's applicability to Intelligent Transport System (ITS). As one of main transportation methods, by using WAVE, quality of railroad communication including WLAN based Communication Based Train Control (CBTC) can be enhanced and variety of railroad communication systems can be integrated into WAVE. However, there are technical challenges to adopt WAVE in railroad communications. For the simplest single-PHY WAVE, time division alternation of 50ms between Control Channel (CCH) and Service Channel (SCH) is required. Since there are delay sensitive railroad traffic types, alternation operation of CCH and SCH may cause performance degradation. In this paper, after identifying a couple of problems based on detailed analysis, a novel packet transmission scheme under railroad environment is proposed. In order to verify if the proposed scheme meets the requirement of railroad communication, WAVE transmission is mathematically modeled.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.23 no.6
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• pp.726-732
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• 2019

In this study, we proposed an asymmetric differential inductor to improve the linearity of differential power amplifiers. Considering the phase error between differential signals of the differential amplifier, the location of the center tap of the differential inductor was modified to minimize the error. As a result, the center tap was positioned asymmetrically inside the differential inductor. With the asymmetric differential inductor, the AM-to-AM and AM-to-PM distortions of the amplifier were suppressed. To confirm the feasibility of the inductor, we designed a 2.4 GHz differential CMOS PA for IEEE 802.11n WLAN applications with a 64-quadrature amplitude modulation (QAM), 9.6 dB peak-to-average power ratio (PAPR), and a bandwidth of 20 MHz. The designed power amplifier was fabricated using the 180-nm RF CMOS process. The measured maximum linear output power was 17 dBm, whereas EVM was 5%.

• Journal of Advanced Navigation Technology
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• v.14 no.3
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• pp.328-335
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• 2010

In this paper, an efficient algorithm and area-efficient hardware architecture have been proposed for $2{\times}2$ MIMO-OFDM based WLAN baseband modem with two transmit and two receive antennas. To enhance the performance of the receiver, the efficient timing synchronization algorithm and symbol detector based on MML algorithm are presented. Also, by sharing the hardware block with multi-stage pipeline structure and using the complex multiplier based on polar-coordinate, the complexity of the proposed architecture is dramatically decreased. The proposed area-efficient hardware design was designed in hardware description language (HDL) and synthesized to gate-level circuits using 0.13um CMOS standard cell library. As a result, the complexity of the proposed modem receiver is reduced by 56% over the conventional architecture.