• Journal of IKEEE
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• v.22 no.2
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• pp.510-513
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• 2018

Recently, EMC (electromagnetic compatibility) becomes very important, which demands the measurement of EMI (electromagnetic interference) in the chip level. NFS (near-field scanning) systems defined in IEC 61967 and IEC 62508 are typical methods to analyze EMI in the chip level. As chips becomes faster, frequency measurement of NFS system should become wideband, but it degrades SNR (singal-to-noise ratio) of the NFP (near-field probe). This paper surveys SNR enhancement technologies of the NFS while maintaining wideband characteristics.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.49 no.6
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• pp.25-34
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• 2012

New calibration method for the near-field scanning (NFS) system is presented. The proposed calibration method consisted of a new near-field antenna (NFP) and newly devised patterns as circular patch patterns (CPPs) and meander patterns (MPs). The proposed patterns were used for improving spatial resolutions and simplifying a calibration procedure of the NFP compared to the conventional method defined in the IEC61967-3 and 6. Also, the effect of the length of NFPs on attenuation characteristics was investigated with length of 8mm and 30mm. For them, we designed and fabricated CPPs of diameter (D) = 20, 40, 60, and 100mm and MPs of various widths and spaces. We found the reverse relations between spatial resolutions and heights of measuring points by using simplified calibration procedure. The testing result shows that the spatial resolution of $120{\mu}m$ at height of $200{\mu}m$ was verified without complex correlation algorithms under 8GHz. For manufacturing cost all patterns and the NFP were realized with low-cost fabrication using PCB (FR-4) not by a conventional LTCC process. For verification of chip-level EMC from the results, near-field scanning system (NFSS) having step resolution of Sub-micron scale was produced and by using the proposed NFSS and proposed NFP measurement of chip shows accurately the shape of the resolution of $200{\mu}m$ patterns for securing a high level of chip-level EMC verification.

• Journal of IKEEE
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• v.21 no.3
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• pp.272-275
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• 2017

Recently, semiconductor integration density enormously increases and its interconnection width is significantly narrowed, which leads to EMI (electromagnetic interference) problems on chip level. Chip manufacturer exploits TEM cell (transverse electromagnetic cell) to measure EMI on chip level, which requires PCB (printed circuit board) for measurement purpose. However, it is often neglected to consider that PCB patterns and other factors can affect on EMI measurement. In this paper, several test patterns are designed for different PCB design variables, and effects of PCB patterns on EMI measurement in TEM cell are analyzed. Based on these analyses, PCB design guidelines are also proposed to minimize the effects on EMI measurements.