• Title/Summary/Keyword: IEC 61967

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Enhancement Technologies of Signal-to-Noise Ratio in the Near-Field Scanning Systems (근거리 전자장 스캐닝 시스템의 잡음 대 성능 비 향상 기술)

  • Shin, Youngsan;Lee, Seongsoo
    • Journal of IKEEE
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    • v.22 no.2
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    • pp.510-513
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    • 2018
  • Recently, EMC (electromagnetic compatibility) becomes very important, which demands the measurement of EMI (electromagnetic interference) in the chip level. NFS (near-field scanning) systems defined in IEC 61967 and IEC 62508 are typical methods to analyze EMI in the chip level. As chips becomes faster, frequency measurement of NFS system should become wideband, but it degrades SNR (singal-to-noise ratio) of the NFP (near-field probe). This paper surveys SNR enhancement technologies of the NFS while maintaining wideband characteristics.

Analysis for Shielding Effectiveness of Metal Shielding Layer within Near-Field of Noise Source (노이즈 소스 근거리장에 위치한 금속 차폐막의 차폐효과 분석)

  • Lee, Won-Seon;Lee, Won-Hui;Hur, Jung
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.19 no.3
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    • pp.59-65
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    • 2019
  • The EMI shielding effectiveness of the shielding layer thickness was analyzed when the metal shielding layer was placed in the near field of the magnetic probe and the noise source. Microstrip lines were used as noise source, and graphite and ferrite were selected as metal shielding materials. The magnetic probe uses the electromagnetic radiation measurement method using the magnetic probe by applying the IEC 61967-6 method. The transmission coefficient between the microstrip line and the magnetic probe was analyzed. The distance between the two was 1 mm for a single shielding layer and 5 mm for a multiple shielding layer. The thickness of the shielding layer was changed to 5 um, 10 um, 30 um, and 50 um. When the frequency was changed from 150 kHz to 1 GHz, a maximum shielding effectiveness (SE) of 44.9 dB was obtained.

Chip-level NFP Calibration and Verification Using Improved Probe for NFS Standardization (NFS 표준을 위한 개선된 프로브를 이용한 칩 수준 NFP 측정값 교정 및 검증)

  • Lee, Pil-Soo;Wee, Jae-Kyung;Kim, Boo-Gyoun;Choi, Jai-Hoon;Yeo, Soon-Il
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.49 no.6
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    • pp.25-34
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    • 2012
  • New calibration method for the near-field scanning (NFS) system is presented. The proposed calibration method consisted of a new near-field antenna (NFP) and newly devised patterns as circular patch patterns (CPPs) and meander patterns (MPs). The proposed patterns were used for improving spatial resolutions and simplifying a calibration procedure of the NFP compared to the conventional method defined in the IEC61967-3 and 6. Also, the effect of the length of NFPs on attenuation characteristics was investigated with length of 8mm and 30mm. For them, we designed and fabricated CPPs of diameter (D) = 20, 40, 60, and 100mm and MPs of various widths and spaces. We found the reverse relations between spatial resolutions and heights of measuring points by using simplified calibration procedure. The testing result shows that the spatial resolution of $120{\mu}m$ at height of $200{\mu}m$ was verified without complex correlation algorithms under 8GHz. For manufacturing cost all patterns and the NFP were realized with low-cost fabrication using PCB (FR-4) not by a conventional LTCC process. For verification of chip-level EMC from the results, near-field scanning system (NFSS) having step resolution of Sub-micron scale was produced and by using the proposed NFSS and proposed NFP measurement of chip shows accurately the shape of the resolution of $200{\mu}m$ patterns for securing a high level of chip-level EMC verification.

Effects of PCB Patterns on EMI Measurement in TEM Cell and Proposal of PCB Design Guidelines (TEM 셀에서 PCB 패턴이 EMI 측정에 미치는 영향 및 PCB 설계 가이드라인 제시)

  • Choi, Minkyoung;Shin, Youngsan;Lee, Seongsoo
    • Journal of IKEEE
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    • v.21 no.3
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    • pp.272-275
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    • 2017
  • Recently, semiconductor integration density enormously increases and its interconnection width is significantly narrowed, which leads to EMI (electromagnetic interference) problems on chip level. Chip manufacturer exploits TEM cell (transverse electromagnetic cell) to measure EMI on chip level, which requires PCB (printed circuit board) for measurement purpose. However, it is often neglected to consider that PCB patterns and other factors can affect on EMI measurement. In this paper, several test patterns are designed for different PCB design variables, and effects of PCB patterns on EMI measurement in TEM cell are analyzed. Based on these analyses, PCB design guidelines are also proposed to minimize the effects on EMI measurements.