• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2002.07a
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• pp.32-35
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• 2002

The work focuses on the development of a Cu lead-frame with a single-sided adhesive tape for cost reduction and reliability improvement of LOC (lead on chip) package products, which are widely used for the plastic-encapsulation of memory chips. Most of memory chips are assembled by the LOC packaging process where the top surface of the chip is directly attached to the area of the lead-frame with a double-sided adhesive tape. However, since the lower adhesive layer of the double-sided adhesive tape reveals the disparity in the coefficient of thermal expansion from the silicon chip by more than 20 times, it often causes thermal displacement-induced damage of the IC pattern on the active chip surface during the reliability test. So, in order to solve these problems, in the resent work, the double-sided adhesive tape is replaced by a single-sided adhesive tape. The single-sided adhesive tape does net include the lower adhesive layer but instead, uses adhesive materials, which are filled in clear holes of the base film, just for the attachment of the lead-frame to the top surface of the memory chip. Since thermal expansion of the adhesive materials can be accommodated by the base film, memory product packaged using the lead-flame with the single-sided adhesive tape is shown to have much improved reliability. Author allied this invention to the Korea Patent Office for a patent (4-2000-00097-9).

• Journal of Industrial Technology
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• v.27 no.B
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• pp.9-14
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• 2007

In this paper, four types of igniters were modeled and their characteristics were researched. And then we analyzed and experimented the effect on the control IC operation in this system. Due to the high ignition voltage, the DC power line on control IC is contaminated with the impulsive noise voltage. So the control IC operation is stopped. Therefore we have found that contamination of DC power noise is reduced by shielding, grounding pattern, and filtering method. We showed that the experimental results are agreed with the theoritical value obtained by the four types of ignitor models.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.4
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• pp.120-126
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• 1989

IC chip layout pattern recognition algorithms using image processing techniques are being developed for the automation of manufacturing and inspecting chips. Recognitioin of chip pattern requires feature extraction from nach rrame of chip image adn needs to match the feature data through all frames. In this paper, vertex position and form having layout information are extracted by the feature straightening algorithm, and global coordinates of layout pattern are extracted by the feature straightening algorithm, and global coordinates of layout pattern are obtainnd by vertex form matching from the overlapped area of neighbour frame.

• Journal of Korea Multimedia Society
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• v.12 no.1
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• pp.107-121
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• 2009

First reason for generation of standby power is because starting voltage must pass through from the source of electricity to IC. The second reason is due to current when IC is in operation. Purpose of this abstract is on structures of simple modules that automatically switch on or off through analysis of state on standby power and analysis of cutoff point patterns as well as application of algorithms. To achieve this, this paper is based on analysis of electric signals and modeling. Also, on/off cutoff criteria has been established for reduction of standby power. To find on/off cutoff point, that is executed algorithm of similar group and leading pattern group generation in the standby power state. Therefore, the algorithm was defined as an important parameter of the subtraction value of calculated between $1^{st}$ SCS, $2^{nd}$ SCS, and the median value of sampling coefficient per second from a wall outlet.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1065-1068
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• 1998

This paper proposes a new test generation method. Most of the test generation methods are gate-level based, but our scheme is VHDL based, especially in other word, behavioral-level based. Our test pattern generation method uses software test method. And we generate deterministic test pattern with this method. The purpose of our method is to reduce the time and effort to generate the test patterns for the end-product test of IC.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.1005-1008
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• 1998

IC testing plays a very important role in IC manufacturing process. Modern complex ASIC chips making it difficult for gate level and RLT level test generation techniques to generate good test vector in resonable time. In this paper we proposed new test pattern generation method in VHDL description to detect manufacturing faults. This method based on software testing can easily generate test vector and independent to synthesis result.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.41 no.1
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• pp.19-26
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• 2004

In this paper, we suggest a 3D vision inspection method which use only one camera. If we have the database of pattern and can recognize the object, and also estimate the rotated shape of the parts, we can inspect the parts using only one image. We used the 3D database and the 2D geometrical pattern matching, and the rotation transition theory about the algorithm. As the results, we could have the capability of the recognition and inspection of the rotated object through the estimation of rotation an81e. We applied our suggested algorithm to the inspection of typical IC and capacitor, and compared our suggested algorithm with the conventional 2D inspection method and the feature space trajectory method.

• Journal of Internet of Things and Convergence
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• v.6 no.1
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• pp.97-102
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• 2020

Multi-Channel Switch ICs for IoT have integrated several solid state structure low ON-resistance bi-directional relay MOS switches with level shifter to drive high voltage and they should be independently controlled by external serialized logic control. These devices are designed for using in applications requiring high-voltage switching control by low-voltage control signals, such as medical ultra-sound imaging, ink-jet printer control, bare board open/short and leakage test system using Kelvin 4-terminal measurement method. This paper describes implementation of analog switch control block and its verification using Field programmable Gate Array (FPGA) test pattern generation. Each block has been implemented using Verilog hardware description language then simulated by Modelsim and prototyped in a FPGA board. Compare to conventional IC, The proposed architecture can be applied to fields where multiple entities need to be controlled simultaneously in the IoT environment and the proposed pattern generation method can be applied to test similar types of ICs.

• Journal of the Korean Society of Food Science and Nutrition
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• v.32 no.7
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• pp.1120-1125
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• 2003

Bioactive properties of low molecular weight peptides purified from anchovy sauce fermented in underground at 15$\pm$3$^{\circ}C$ for 1, 3, and 5 years, respectively, were investigated. The fermented anchovy sauce for 1 year showed 3 peaks on gel permeation chromatography pattern, while 3 and 5 year fermented anchovy sauce showed 4 and 5 peaks, respectively. The longer fermentation period, the lower molecular weight of peptides on gel permeation chromatography pattern. Antioxidative, antitumor, and ACE inhibitory activities of low molecular weight peptides increased as fermentation period increased. Antioxidative and antitumor activities of peptide peak 3 purified from 3 year fermented anchovy sauce were the highest with 34 and 44 $\mu\textrm{g}$/mL of $IC_{50}$/ values, respectively, while ACE inhibitory activity ($IC_{50}$/, 32 $\mu\textrm{g}$/mL) of peak 3 purified from 1 year fermented was the highest.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.33A no.5
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• pp.203-211
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• 1996

This paper describes CAD tools for the construction of image database in IC chip analysis CAD system. For IC chip analysis by high-resolution microscopy, the image database is essential to manage more than several thousand images. But manual database construction is error-prone and time-consuming. In order to solve this problem, we develop a set of CAD toos that include image grabber to capture chip images, image editor to make the whole chip image database from the grabbed images, and image divider to reconstruct the database that consists of evenly overlapped images for efficient region search. we also develop an interactive pattern matching method for user-friendly image editing, and a heuristic region search method for fast image division. The tools are developed with a high-performance graphic hardware with JPEG image comparession chip to process the huge color image data. The tools are under the field test and experimental resutls show that the database construction time can be redcued in 1/3 compared to manual database construction.