• 전자공학회논문지S
• /
• 제34S권7호
• /
• pp.102-111
• /
• 1997

In this paper, a patern recognition method of surface mount device(SMD) IC using wavelet transform and neural network is proposed. We chose the feature parameter according to the characteristics of coefficient matrix which is obtained from four level discrete wavelet transform (DWT). These feature parameters are normalized and then used for the input vector of neural network which is capable of adapting the surroundings such as variation of illumination, arrangement of objects and translation. Experimental results show that when the same form of feature pattern, as is used for learning, is put into neural network and gained 100% rate ofrecognition irrespective of SMD IC kinds, location and variation of illumination. In the case of unused feature pattern for learning, the recognition rate is 85.9% under the similar surroundings, where as an average recognition rate is 96.87% for the case of reregulated value of illumination. Proosed method is relatively simple compared with the traditional space domain method in extracting the feature parameter and is also well suited for recognizing the pattern's class, position and existence. It can also shorten the processing tiem better than method extracting feature parameter with the use of discrete cosine transform(DCT) and adapt the surroundings such as variation of illumination, the arrangement and the translation of SMD IC.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2004년도 학술대회지
• /
• pp.717-722
• /
• 2004

A design was done, and all characteristic of photodetectr of the web pattern type which a standard process of the Bipolar which Si PIN structure was used in this paper, and was used for the current amplifier design was used, and high-speed, was used as receiving optcal area of high altitude, and the module which had a low dark current characteristic was implemented with one chip with a base. Important area decreases an area of Ie at the time of this in order to consider an electrical characteristic and economy than the existing receiving IC, and performance of a product and confidence are got done in incense. First of all, the receiving IC which a spec, pattern of a wafer to he satisfied with the following electrical optical characteristic that produced receiving IC of 5V and structure are determined, and did one-chip is made. On the other hand, the time when AR layer of double is $Si_{3}N_{4}/SiO_{2}=1500/1800$ has an optical reflectivity of less than $10{\%}$ on an incidence optical wavelength of 660 ,and, in case of photo detector which reverse voltage made with 1.8V runs in 1.65V, an error about a change of thickness is very the thickness that can be improved surely. And, as for the optical current characteristic, about 5 times increases had the optical current with 274nA in 55nA when Pc was -27dBm. A BJT process is used, and receiving IC running electricity suitable for low voltage and an optical characteristic in minimum 1.8V with a base with two phases is made with one chip. IC of low voltage operates in 1.8V and 3.0V at the same time, and optical link receiving IC is going to be implemented

• 한국통신학회논문지
• /
• 제22권3호
• /
• pp.481-492
• /
• 1997

This paper presents an algorithm for recognizing surface mount device(SMD) IC pattern based on the error back propoagation(EBP) neural network and discrete cosine transform(DCT). In this approach, we chose such parameters as frequency, angle, translation and amplitude for the shape informantion of SMD IC, which are calculated from the coefficient matrix of DCT. These feature parameters are normalized and then used for the input vector of neural network which is capable of adapting the surroundings such as variation of illumination, arrangement of objects and translation. Learning of EBP neural network is carried out until maximum error of the output layer is less then 0.020 and consequently, after the learning of forty thousand times, the maximum error have got to this value. Experimental results show that the rate of recognition is 100% in case of the random pattern taken at a similar circumstance as well as normalized training pattern. It also show that proposed method is not only relatively relatively simple compare with the traditional space domain method in extracting the feature parameter but also able to re recognize the pattern's class, position, and existence.

• 한국산학기술학회논문지
• /
• 제21권1호
• /
• pp.8-13
• /
• 2020

IC 패키지와 같이 두께가 수백 마이크로미터 정도로 매우 얇은 기판에서 뒤틀림 불량을 일으키는 가장 큰 원인은 응력이다. 일반적으로 응력은 기판 위에 서로 다른 물질을 적층할 때, 결정구조 및 그에 따른 열팽창 계수의 차이로 인해 발생한다. 본 연구에서는 사각형의 박막 패턴이 적층된 기판에 발생하는 응력의 거동을 수치적으로 분석하였다. 먼저 기판 변위를 구하고, 이를 이용하여 기판 변형률과 응력을 구하였다. 박막 패턴의 가장자리에 인장력이 집중된 경우, 박막 패턴의 가장자리를 중심으로 수직 응력과 전단 응력이 발생한다. 수직 응력은 박막 패턴의 가장자리와 꼭짓점 부근에 발생한다. 전단 응력도 박막 패턴의 가장자리를 중심으로 발생하나 수직 응력과는 달리 꼭짓점 부근에는 나타나지 않는다. 또한 가장자리를 중심으로 전단 응력의 크기와 방향이 바뀌는 것을 확인할 수 있었다. 박막패턴 가장자리 힘이 동일할 때, 수직 응력은 전단 응력에 비해 10배 정도의 값을 나타내었다. 이는 뒤틀림 불량을 일으키는 가장 큰 원인이 수직 응력임을 나타낸다.

• 한국ITS학회 논문지
• /
• 제13권2호
• /
• pp.1-11
• /
• 2014

본 논문의 목적은 DSRC 기반 통행속도 이력데이터를 활용하여 IC-IC 구간 단위의 통행패턴을 도출하는 것이며, 이를 통해 방대한 이력정보 데이터의 활용도를 높이고, 단순하지만 정확성 높은 방법으로 도로의 통행패턴을 용이하게 파악할 수 있게 하는 것이다. 통행패턴 분류는 의사결정나무 기법을 적용하였고, 월 시간대 구간 단위로 분리된 통행패턴을 생성하여 시 공간이 변화되어도 이에 대응 가능하도록 하였다. 경부고속도로 서울TG~안성IC 구간을 대상으로 의사결정나무 기법을 적용한 결과, 요일 기준으로 (월)(화 수 목)(금)(토)(일) 5개 그룹으로 고정 통행패턴이 분류되었다. 분류 결과를 영동, 중부, 중부내륙 고속도로의 9개 구간에 적용하여 통계적 검증을 수행한 결과 약 93%의 적합도를 갖는 것으로 나타났다. 의사결정나무를 통한 통행패턴 오차를 개선하기 위하여 4개의 추가변수를 도입한 결과, "직전월의 소통상황"을 설명변수로 추가할 경우 통행속도 분산이 약 50% 감소함을 확인하였고, 실제 상황에 적용할 경우 소통 원활 시의 오차가 약 4% 감소되었다.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 1988년도 전기.전자공학 학술대회 논문집
• /
• pp.553-556
• /
• 1988

Recognition of IC chip pattern requires extraction of features, which have the information of vertex position and orientation. Edges are extracted and straightening algorithm is applied to the edges, so that lines are obtained. With these extracted data, the coordinate and orientation of all vertices are extracted and vertex-form matching is applied to the locally overlapped area of neighborhood frames to have global coordinate of IC chip.

• 전기학회논문지
• /
• 제64권4호
• /
• pp.592-597
• /
• 2015

3D-IC is a novel semiconductor packaging technique stacking dies to improve the performance as well as the overall size. TSV is ideal for 3D-IC because it is convenient for stacking and excellent in electrical characteristics. However, due to high-density and micro-size of TSVs, they should be tested with a non-invasive manner. Thus, we introduce a TSV test method on test prober without a direct contact in this paper. A capacitive coupling effect between a probe tip and TSV is used to discriminate small TSV faults like voids and pin-holes. Through EM simulation, we can verify the size of eye-patterns with various frequencies is good for TSV test tools and non-contact test will be promising.

• 대한전기학회:학술대회논문집
• /
• 대한전기학회 2003년도 하계학술대회 논문집 D
• /
• pp.2489-2491
• /
• 2003

In this study, we implement the laser pattern controller using function generator IC. Overall system consists of : (1) laser excitation circuit and laser tube, (2) two small mirrors to reflect laser beam on the screen, (3) two small motors for X, Y axis enabling each attached mirrors to rotate, (4) controller for motor control and user interface, (5) system power. We explain the architecture of the system and required theory to implement the system. Finally, experimental results are illustrated to show the performance of the system.

• Journal of Welding and Joining
• /
• 제30권3호
• /
• pp.26-31
• /
• 2012

Three-dimensional integrated circuit (3D IC) technology has become increasingly important due to the demand for high system performance and functionality. We have evaluated the effect of Buffered oxide etch (BOE) on the interfacial bonding strength of Cu-Cu pattern direct bonding. X-ray photoelectron spectroscopy (XPS) analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE 2min. Two 8-inch Cu pattern wafers were bonded at $400^{\circ}C$ via the thermo-compression method. The interfacial adhesion energy of Cu-Cu bonding was quantitatively measured by the four-point bending method. After BOE 2min wet etching, the measured interfacial adhesion energies of pattern density for 0.06, 0.09, and 0.23 were $4.52J/m^2$, $5.06J/m^2$ and $3.42J/m^2$, respectively, which were lower than $5J/m^2$. Therefore, the effective removal of Cu surface oxide is critical to have reliable bonding quality of Cu pattern direct bonds.

• 한국정밀공학회:학술대회논문집
• /
• 한국정밀공학회 2012년도 춘계학술대회 논문집
• /
• pp.127-128
• /
• 2012