• Journal of the Korean Institute of Telematics and Electronics S
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• v.34S no.7
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• pp.102-111
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• 1997

In this paper, a patern recognition method of surface mount device(SMD) IC using wavelet transform and neural network is proposed. We chose the feature parameter according to the characteristics of coefficient matrix which is obtained from four level discrete wavelet transform (DWT). These feature parameters are normalized and then used for the input vector of neural network which is capable of adapting the surroundings such as variation of illumination, arrangement of objects and translation. Experimental results show that when the same form of feature pattern, as is used for learning, is put into neural network and gained 100% rate ofrecognition irrespective of SMD IC kinds, location and variation of illumination. In the case of unused feature pattern for learning, the recognition rate is 85.9% under the similar surroundings, where as an average recognition rate is 96.87% for the case of reregulated value of illumination. Proosed method is relatively simple compared with the traditional space domain method in extracting the feature parameter and is also well suited for recognizing the pattern's class, position and existence. It can also shorten the processing tiem better than method extracting feature parameter with the use of discrete cosine transform(DCT) and adapt the surroundings such as variation of illumination, the arrangement and the translation of SMD IC.

• Proceedings of the IEEK Conference
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• 2004.08c
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• pp.717-722
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• 2004

A design was done, and all characteristic of photodetectr of the web pattern type which a standard process of the Bipolar which Si PIN structure was used in this paper, and was used for the current amplifier design was used, and high-speed, was used as receiving optcal area of high altitude, and the module which had a low dark current characteristic was implemented with one chip with a base. Important area decreases an area of Ie at the time of this in order to consider an electrical characteristic and economy than the existing receiving IC, and performance of a product and confidence are got done in incense. First of all, the receiving IC which a spec, pattern of a wafer to he satisfied with the following electrical optical characteristic that produced receiving IC of 5V and structure are determined, and did one-chip is made. On the other hand, the time when AR layer of double is $Si_{3}N_{4}/SiO_{2}=1500/1800$ has an optical reflectivity of less than $10{\%}$ on an incidence optical wavelength of 660 ,and, in case of photo detector which reverse voltage made with 1.8V runs in 1.65V, an error about a change of thickness is very the thickness that can be improved surely. And, as for the optical current characteristic, about 5 times increases had the optical current with 274nA in 55nA when Pc was -27dBm. A BJT process is used, and receiving IC running electricity suitable for low voltage and an optical characteristic in minimum 1.8V with a base with two phases is made with one chip. IC of low voltage operates in 1.8V and 3.0V at the same time, and optical link receiving IC is going to be implemented

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.481-492
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• 1997

This paper presents an algorithm for recognizing surface mount device(SMD) IC pattern based on the error back propoagation(EBP) neural network and discrete cosine transform(DCT). In this approach, we chose such parameters as frequency, angle, translation and amplitude for the shape informantion of SMD IC, which are calculated from the coefficient matrix of DCT. These feature parameters are normalized and then used for the input vector of neural network which is capable of adapting the surroundings such as variation of illumination, arrangement of objects and translation. Learning of EBP neural network is carried out until maximum error of the output layer is less then 0.020 and consequently, after the learning of forty thousand times, the maximum error have got to this value. Experimental results show that the rate of recognition is 100% in case of the random pattern taken at a similar circumstance as well as normalized training pattern. It also show that proposed method is not only relatively relatively simple compare with the traditional space domain method in extracting the feature parameter but also able to re recognize the pattern's class, position, and existence.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.21 no.1
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• pp.8-13
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• 2020

Stress is the main cause of warpage failure of very thin substrates with thickness of several hundred ㎛, such as IC packages. Stress usually results from differences in crystal structures and corresponding thermal expansion coefficients when depositing different substances on a substrate. In this study, the behaviors of stress occurring in substrates were numerically analyzed by the thin-film pattern of the rectangles stacked on the substrates. First, the substrate displacement was obtained and the substrate strain and stress were obtained using it. When the tensile force is concentrated at the edge of the thin film pattern, normal and shear stresses are generated around the edge of the thin film pattern. Normal stress occurs near the edges of the thin film pattern and the vertexes. Shear stress also occurs around the edge of the thin film pattern, but unlike normal stress, it does not appear near the vertexes. It was also confirmed that the magnitude and direction of shear stress are changed around the edge. When edge forces of thin-film pattern are equal, the normal stress was about 10 times larger than the shear stress. This indicates that normal stress is the biggest cause of warpage failure.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.13 no.2
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• pp.1-11
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• 2014

In this paper, travel speed patterns were deducted based on historical DSRC travel speed data using Decision Tree technique to improve availability of the massive amount of historical data. These patterns were designed to reflect spatio-temporal vicissitudes in reality by generating pattern units classified by months, time of day, and highway sections. The study area was from Seoul TG to Ansung IC sections on Gyung-bu highway where high peak time of day frequently occurs in South Korea. Decision Tree technique was applied to categorize travel speed according to day of week. As a result, five different pattern groups were generated: (Mon)(Tue Wed Thu)(Fri)(Sat)(Sun). Statistical verification was conducted to prove the validity of patterns on nine different highway sections, and the accuracy of fitting was found to be 93%. To reduce travel pattern errors against individual travel speed data, inclusion of four additional variables were also tested. Among those variables, 'traffic condition on previous month' variable improved the pattern grouping accuracy by reducing 50% of speed variance in the decision tree model developed.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.553-556
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• 1988

Recognition of IC chip pattern requires extraction of features, which have the information of vertex position and orientation. Edges are extracted and straightening algorithm is applied to the edges, so that lines are obtained. With these extracted data, the coordinate and orientation of all vertices are extracted and vertex-form matching is applied to the locally overlapped area of neighborhood frames to have global coordinate of IC chip.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.64 no.4
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• pp.592-597
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• 2015

3D-IC is a novel semiconductor packaging technique stacking dies to improve the performance as well as the overall size. TSV is ideal for 3D-IC because it is convenient for stacking and excellent in electrical characteristics. However, due to high-density and micro-size of TSVs, they should be tested with a non-invasive manner. Thus, we introduce a TSV test method on test prober without a direct contact in this paper. A capacitive coupling effect between a probe tip and TSV is used to discriminate small TSV faults like voids and pin-holes. Through EM simulation, we can verify the size of eye-patterns with various frequencies is good for TSV test tools and non-contact test will be promising.

• Proceedings of the KIEE Conference
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• 2003.07d
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• pp.2489-2491
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• 2003

In this study, we implement the laser pattern controller using function generator IC. Overall system consists of : (1) laser excitation circuit and laser tube, (2) two small mirrors to reflect laser beam on the screen, (3) two small motors for X, Y axis enabling each attached mirrors to rotate, (4) controller for motor control and user interface, (5) system power. We explain the architecture of the system and required theory to implement the system. Finally, experimental results are illustrated to show the performance of the system.

• Journal of Welding and Joining
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• v.30 no.3
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• pp.26-31
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• 2012

Three-dimensional integrated circuit (3D IC) technology has become increasingly important due to the demand for high system performance and functionality. We have evaluated the effect of Buffered oxide etch (BOE) on the interfacial bonding strength of Cu-Cu pattern direct bonding. X-ray photoelectron spectroscopy (XPS) analysis of Cu surface revealed that Cu surface oxide layer was partially removed by BOE 2min. Two 8-inch Cu pattern wafers were bonded at $400^{\circ}C$ via the thermo-compression method. The interfacial adhesion energy of Cu-Cu bonding was quantitatively measured by the four-point bending method. After BOE 2min wet etching, the measured interfacial adhesion energies of pattern density for 0.06, 0.09, and 0.23 were $4.52J/m^2$, $5.06J/m^2$ and $3.42J/m^2$, respectively, which were lower than $5J/m^2$. Therefore, the effective removal of Cu surface oxide is critical to have reliable bonding quality of Cu pattern direct bonds.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2012.05a
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• pp.127-128
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• 2012