• Title/Summary/Keyword: IC Package

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Novel Bumping and Underfill Technologies for 3D IC Integration

  • Sung, Ki-Jun;Choi, Kwang-Seong;Bae, Hyun-Cheol;Kwon, Yong-Hwan;Eom, Yong-Sung
    • ETRI Journal
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    • v.34 no.5
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    • pp.706-712
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    • 2012
  • In previous work, novel maskless bumping and no-flow underfill technologies for three-dimensional (3D) integrated circuit (IC) integration were developed. The bumping material, solder bump maker (SBM) composed of resin and solder powder, is designed to form low-volume solder bumps on a through silicon via (TSV) chip for the 3D IC integration through the conventional reflow process. To obtain the optimized volume of solder bumps using the SBM, the effect of the volumetric mixing ratio of resin and solder powder is studied in this paper. A no-flow underfill material named "fluxing underfill" is proposed for a simplified stacking process for the 3D IC integration. It can remove the oxide layer on solder bumps like flux and play a role of an underfill after the stacking process. The bumping process and the stacking process using the SBM and the fluxing underfill, respectively, for the TSV chips are carefully designed so that two-tier stacked TSV chips are sucessfully stacked.

Fabrication of IC Chip for Self-Diagnostic Function of a Eight-Beam Piezoresistive Accelerometer. (8빔 압저항형 가속도센서의 자기진단 기능을 위한 IC칩 제조)

  • Park, Chang-Hyun;Jun, Chan-Bong;Kang, Hee-Suk;Kim, Jong-Jib;Lee, Won-Tae;Sim, Jun-Hwan;Kim, Dong-Kwon;Lee, Jong-Hyun
    • Journal of Sensor Science and Technology
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    • v.8 no.1
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    • pp.38-44
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    • 1999
  • In this paper, we have constructed a self-diagnostic circuit which could detect erroneous signals in most cases that a eight-beam piezoresistive accelerometer were destroyed more than its one beam. To confirm the function of the circuit, PSPICE simulation was carried out. An IC chip was fabricated with a layout of KA 324 amplifier using a bipolar standard processing. After a package of the chip was sealed using a plastic package with 24 pins, the self-diagnostic characteristics were investigated. Then, the measured self-diagnostic characteristics of the circuit were compared with the PSPICE simulated result.

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Antifuse Circuits and Their Applicatoins to Post-Package of DRAMs

  • Wee, Jae-Kyung;Kook, Jeong-Hoon;Kim, Se-Jun;Hong, Sang-Hoon;Ahn, Jin-Hong
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.1 no.4
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    • pp.216-231
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    • 2001
  • Several methods for improving device yields and characteristics have been studied by IC manufacturers, as the options for programming components become diversified through the introduction of novel processes. Especially, the sequential repair steps on wafer level and package level are essentially required in DRAMs to improve the yield. Several repair methods for DRAMs are reviewed in this paper. They include the optical methods (laser-fuse, laser-antifuse) and the electrical methods (electrical-fuse, ONO-antifuse). Theses methods can also be categorized into the wafer-level(on wafer) and the package-level(post-package) repair methods. Although the wafer-level laser-fuse repair method is the most widely used up to now, the package-level antifuse repair method is becoming an essential auxiliary technique for its advantage in terms of cost and design efficiency. The advantages of the package-level antifuse method are discussed in this paper with the measured data of manufactured devices. With devices based on several processes, it was verified that the antifuse repair method can improve the net yield by more than 2%~3%. Finally, as an illustration of the usefulness of the package-level antifuse repair method, the repair method was applied to the replica delay circuit of DLL to get the decrease of clock skew from 55ps to 9ps.

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Novel Extraction Method for Unknown Chip PDN Using De-Embedding Technique (De-Embedding 기술을 이용한 IC 내부의 전원분배망 추출에 관한 연구)

  • Kim, Jongmin;Lee, In-Woo;Kim, Sungjun;Kim, So-Young;Nah, Wansoo
    • The Journal of Korean Institute of Electromagnetic Engineering and Science
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    • v.24 no.6
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    • pp.633-643
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    • 2013
  • GDS format files, as well as layout of the chip are noticeably needed so as to analyze the PDN (Power Delivery Network) inside of IC; however, commercial IC in the market has not supported design information which is layout of IC. Within this, in terms of IC having on-chip PDN, characteristic of inside PDN of the chip is a core parameter to predict generated noise from power/ground planes. Consequently, there is a need to scrutinize extraction method for unknown PDN of the chip in this paper. To extract PDN of the chip without IC circuit information, the de-embedding test vehicle is fabricated based on IEC62014-3. Further more, the extracted inside PDN of chip from de-embedding technique adopts the Co-simulation model which composes PCB, QFN (Quad-FlatNo-leads) Package, and Chip for the PDN, applied Co-simulation model well corresponds with impedance from measured S-parameters up to 4 GHz at common measured and simulated points.

Some Chemical Properties and Composition of Lipid Extracts of Riced Dehydrated Potato Granules (감자분말(粉末)의 지방질조성(脂肪質組成)과 저장중(貯藏中)의 변화(變化)에 관(關한) 연구(硏究))

  • Yoon, Jeong-Won;Hong, Bum-Shik;Yang, Han-Chul;Kim, Dong-Hoon
    • Korean Journal of Food Science and Technology
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    • v.10 no.3
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    • pp.320-330
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    • 1978
  • Riced dehydrated potato granules with a good reconstituton quality was made from Irish Cobber (IC) and Shimabara which are representative varieties in Korea. A part of IC potato granules was packed in small vinyl-bags while the rest, including some BHA (75ppm)-treated granules, was packed in $301{\times}407$ plain tin cans. These granules were stored in a room at room temperature, and their physico-chemical properties and lipid composition were studied. The color of the granules was measured with a Hunter-type Tristimules colorimeter. L, $a_L,$ and $b_L-values$ were respectively 83.8, -1.1 and 18.3. Variety and package-type did not affect the color. In general, it was darker than that of commercial wheat flour, but whiter than that of commercial defatted soy flour. At $100^{\circ}C$, the granules, irrespective of variety and package-type, absorbed water rapidly, and reached the maximum moisture content of $90{\sim}92%$ in 3 min., whereas they absorbed water more slowly at $8{\sim}14^{\circ}C$, and reached the maximum content of $72{\sim}74%$ in 5 minutes. Peroxide, TBA, carbonyl, acid, and iodine values of the granules after 3 months storage were respetively $150{\sim}460\;meq/kg,\;20{\sim}26,\;154{\sim}380$ micromole, $24{\sim}59,\;and\;70{\sim}78$. Except iodine values, all the chemical values were affected by variety and package-type. Ether and $CHCl_3-extracts$ of the granules from IC and Shimabara were subjected to GLC and TLC analyses. In case of IC, the major fatty acids were palmitic, stearic, and oleic (30.0, 18.8, 40.6), while in case of Shimabara they were palmitic, oleic, and linoleic acids (26.7, 39.6, 23.4%). The major lipid classes were, in both cases, triglycerides and phospholipids. Their contents were raspectively 19.1 and 43.1 (IC), and 30.1 and 37.4% (Shimabara).

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Development of the Integral LED Package Board Power Supply Circuits for Noise Cancellation (일체형 LED Package Board의 노이즈 제거 및 간소화된 전원 공급 회로 개발)

  • Yu, Young-Jin;Park, Jong-Chan
    • The Transactions of the Korean Institute of Electrical Engineers P
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    • v.60 no.2
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    • pp.72-75
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    • 2011
  • In this paper, the voltage across the LED system supplied by positive voltage of power supply system the power consumption of the LED itself, and uses a lot of transformers and analog devices, such as converter startup problems and constant temperature even when the voltage driving abnormally LED current in the destruction caused by the flow of a lot of problems can occur. In this paper, we obtain the technology of consistent current using PWM(pulse width modulation) mode in order to minimize analog devices and eventually discuss the technology to develop consistent output converter using power drive IC.

시선집중, 선진안전사업장 - '안전보건'은 기업 성장을 위한 필수조건, 철저한 안전관리시스템으로 무재해사업장 구현한 스테코(주)

  • Im, Dong-Hui
    • The Safety technology
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    • no.190
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    • pp.21-23
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    • 2013
  • 스테코(주)는 삼성의 최첨단 반도체 조립기술과 일본 TORAY의 베이스필름 기술의 전략적 제휴로, 1995년 설립된 LCD 구동 IC제조업체다. 응용제품으로 노트북PC, LCD, PDP TV, LCD모니터, 핸드폰 등의 액정 판넬을 구동시키는 반도체를 제조하고 있으며, LDI제품 Package 전문반도체 회사로는 세계 최고의 생산성과 기술력을 보유하고 있다는 평가를 받고 있다. 이곳은 18년의 LDI Package경험, 지속적인 연구개발 노력, 그리고 최고 수준의 품질로 비메모리 반도체 제품 분야에서는 전례를 찾기 힘든 경영성과를 달성했다. 2007년과 2008년에 국가생산성대상을 수상한 것이 이를 뒷받침한다. 이러한 기업성장의 원동력은 안전보건에서 찾을 수 있다. 2008년 산업보건 우수사례발표대회 금상, 2010년 무재해사업장 우수사례발표대회 은상, 2009년에는 제8회 대한민국안전대상에서 행정안전부장과의 영예를 안았다. 또한 그 시기 OHSAS18001 및 ISO 14001 인증도 취득하고, 최근에는 무재해 10배수라는 대기록을 달성하면서 명실상부한 최고의 아전기업을 자리 잡게 됐다. 이렇듯 스테코(주)는 빠른 시간 안에 기업반전과 안전보건이라는 두 마리 토끼를 모두 잡으면서 지역 산업현장의 모범이 되고 있는 사업장이다. 스테코(주)를 찾아가 기업발전의 토대가 되고 있는 안전보건활동이 어떻게 이뤄지고 있는지 살펴봤다.

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미세 피치를 갖는 bare-chip 공정 및 시스템 개발

  • 강희석;정훈;조영준;김완수;강신일;심형섭
    • Proceedings of the Korean Society Of Semiconductor Equipment Technology
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    • 2005.05a
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    • pp.79-83
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    • 2005
  • IT 기술, 반도체 산업 등의 급격한 발전에 힘입어 최근의 첨단 전자, 통신제품은 초경량 초소형화와 동시에 고기능 복합화의 발전 추세를 보이고 있다. 이런 추세에 발맞추어 전자제품, 통신제품의 핵심적인 부품인 IC chip도 소형화되고 있다. IC chip 패키징 기술의 하나인 Filp Chip Package는 Module Substrate 위에 Chip Surface를 Bumping 시킴으로서 최단의 접속길이와 저열저항, 저유전율의 특성도 가지면서 초소형에 높은 수율의 저 원가생산성을 갖는 첨단의 패키징 기술이다. 이런 패키징 기술은 수요증가와 더불어 폭발적으로 늘어나고 있으나 까다로운 공정기술에 의해 아직 여러 회사에서 장비가 출시되고 있지 못한 상태이다. 이에 본 연구에서는 최근 수요가 증가하는 LCD Driver IC용 COF 장비를 위한 Flip chip Bonding 장비 및 시스템을 설계, 제작하였다.

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Giga-Hertz-Level Electromagnetic Field Analysis for Equivalent Inductance Modeling of High-Performance SoC and SiP Designs

  • Yao Jason J.;Chang Keh-Jeng;Chuang Wei-Che;Wang, Jimmy S.
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.5 no.4
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    • pp.255-261
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    • 2005
  • With the advent of sub-90nm technologies, the system-on-chip (SoC) and system-in-package (SiP) are becoming the trend in delivering low-cost, low-power, and small-form-factor consumer electronic systems running at multiple GHz. The shortened transistor channel length reduces the transistor switching cycles to the range of several picoseconds, yet the time-of-flights of the critical on-chip and off-chip interconnects are in the range of 10 picoseconds for 1.5mm-long wires and 100 picoseconds for 15mm-long wires. Designers realize the bottleneck today often lies at chip-to-chip interconnects and the industry needs a good model to compute the inductance in these parts of circuits. In this paper we propose a new method for extracting accurate equivalent inductance circuit models for SPICE-level circuit simulations of system-on-chip (SoC) and system-in-package (SiP) designs. In our method, geometrical meshes are created and numerical methods are used to find the solutions for the electromagnetic fields over the fine meshes. In this way, multiple-GHz SoC and SiP designers can use accurate inductance modeling and interconnect optimization to achieve high yields.

MAGFET Hybrid IC with Frequency Output (주파수 출력을 갖는 MAGFET Hybrid IC)

  • Kim, Si-Hon;Lee, Cheol-Woo;Nam, Tae-Chul
    • Journal of Sensor Science and Technology
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    • v.6 no.3
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    • pp.194-199
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    • 1997
  • When voltage or current gets out of the magnetic sensor as it is, we have often faced the problems such as introduction of noise and loss of voltage. In order to reduce these problems, a 2 drain MAGFET operating in the saturation region and fabricated by CMOS process, the system of I/V converter, VCO with operational amplifier, and V/F conversion circuits with Schmitt Trigger are designed and fabricated in one package. The absolute sensitivity of magnetic sensor shows 1.9 V/T and the product sensitivity is $3.2{\times}10^{4}\;V/A{\cdot}T$. The characteristic of V/F conversion is very stabilized and has the value of 190 kHz/T.

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