• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.6
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• pp.1046-1055
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• 1994

In this paper, to design high speed 1 line VRAM(Video RAM) suitable for image signal processing with ASIC(Application Specific IC) method, the VRAM memory core has been designed using 3-TR dual-port dynamic cell which has excellent access time and integration characteristics. High speed pipeline operation was attained by separating the first row from the subarray 1 memory core and the simultaneous I/Q operation for a selected single address was made possible by adopting data-latch scheme. Peripheral circuits were designed implementing address selector and 1/2V voltage generator. Integrated ASIC has been optimized using 1.5[ m] CMOS design rule.

• Aerospace Engineering and Technology
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• v.3 no.2
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• pp.104-115
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• 2004

In this study, contains Design and Simulation data for Tone filter applied to the KSLV-1 FTS Receiver. Received Signal contains unwanted Noise and Jitter which should be eliminated by any kind of filters. In the design of KSLV-1 FTS Receiver, two different type of filters are used. One is Low-Pass Filter for rejecting high order harmonics and another is Tone Filter for sorting pure original signal in the mixed demodulate Signals. For the purpose of this development, various kinds of filter are studied and simulated for finding adequate type of filter.

• Journal of Power Electronics
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• v.5 no.2
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• pp.129-141
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• 2005

A high-performance robust hybrid speed controller for a permanent-magnet synchronous motor (PMSM) drive with an on-line trained neural-network model-following controller (NNMFC) is proposed. The robust hybrid controller is a two-degrees-of-freedom (2DOF) integral plus proportional & rate feedback (I-PD) with neural-network model-following (NNMF) speed controller (2DOF I-PD NNMFC). The robust controller combines the merits of the 2DOF I-PD controller and the NNMF controller to regulate the speed of a PMSM drive. First, a systematic mathematical procedure is derived to calculate the parameters of the synchronous d-q axes PI current controllers and the 2DOF I-PD speed controller according to the required specifications for the PMSM drive system. Then, the resulting closed loop transfer function of the PMSM drive system including the current control loop is used as the reference model. In addition to the 200F I-PD controller, a neural-network model-following controller whose weights are trained on-line is designed to realize high dynamic performance in disturbance rejection and tracking characteristics. According to the model-following error between the outputs of the reference model and the PMSM drive system, the NNMFC generates an adaptive control signal which is added to the 2DOF I-PD speed controller output to attain robust model-following characteristics under different operating conditions regardless of parameter variations and load disturbances. A computer simulation is developed to demonstrate the effectiveness of the proposed 200F I-PD NNMF controller. The results confirm that the proposed 2DOF I-PO NNMF speed controller produces rapid, robust performance and accurate response to the reference model regardless of load disturbances or PMSM parameter variations.

• Journal of the Korea Institute of Military Science and Technology
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• v.24 no.6
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• pp.610-618
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• 2021

In this paper, a photonic-based microwave system technology is described, and a traveling-wave electro-optic modulator is designed and manufactured as a key component. The fabricated modulator is composed of a metal diffusion waveguide for optical transmission and a planar waveguide electrode on lithium niobate substrate for microwave transmission. The electro-optic response bandwidth of I and Q channels in a fabricated dual parallel Mach-Zehnder modulator were measured for 27.67 and 28.11 GHz, respectively. Photonic four times up-converted X-band frequency and linear frequency modulated signal were confirmed using the fabricated electro-optic modulator by S-band input signal. The confirmed broadband signal can be applied to a microwave system for surveillance and high-resolution ISAR imaging.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.3
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• pp.51-57
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• 2010

A dual-mode direct conversion receiver is developed in $0.13\;{\mu}m$ RF CMOS process for IEEE 802.11n based wireless LAN and IEEE 802.16e based mobile WiMAX application. The RF receiver covers the frequency band between 2.3 and 2.7 GHz. Three-step gain control is realized in LNA by using current steering technique. Current bleeding technique is applied to the down-conversion mixer in order to lower the flicker noise. A frequency divide-by-2 circuit is included in the receiver for LO I/Q differential signal generation. The receiver consumes 56 mA at 1.4 V supply voltage including all LO buffers. Measured results show a power gain of 32 dB, a noise figure of 4.8 dB, a output $P_{1dB}$ of +6 dBm over the entire band.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.10A
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• pp.1571-1578
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• 1999

In this paper, we present the Modulator Channel Card and VLSI chip for the Radio Transceiver Unit (RTU) of direct sequence code division multiple access (DS-CDMA) Wireless Local Loop (WLL) System. The Modulator Channel Card is designed and implemented using ASIC's, FPGA's and DSP's. The ASIC, compliance with Common Air Interface specification proposed by ETRI, has 40K gates which is designed to operate at 32MHz, and is fabricated using $0.6\mu\textrm{m}$ CMOS process. The ASIC carries out for I- or Q- phase data channel signal processing at a time, where each data channel processing consists of channel coding, block interleaving, scrambling, Walsh modulation, Pseudo-Noise (PN) spreading, and baseband filtering. The Modulator Channel Card has been integrated as a part of RTU of WLL system and is confirmed that it meets all functional and performance requirements.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.43 no.12 s.354
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• pp.16-23
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• 2006

This paper presents the development of the fast Direction Finder using direct conversion method, which can intercept for short pulse signal of less' than 1 msec. in RF Down Converter, and CVDF(Correlative Vector Direction Finding) algorithm, which estimates DoA (Direction of Arrival). The configuration and characteristics of direction finder using 5-channel equi-spaced circular array antenna are presented and the direct conversion techniques for removing tuning time using I/Q demodulator are described. The CRLB of our model is derived, the principles of 2 kind of CVDF algorithm are explained and their characteristics are compared with CRLB w.r.t the number of samples and spacing ratio. The RF Down Converter prototype using direct conversion method is manufactured, the 2 kind of CVDF algorithm are applied and their performance are analyzed. Finally it is confirmed the LSE based CVDF algorithm is better than correlation-coefficient based except for ambiguity protection capabilities.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.7
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• pp.844-847
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• 2012

By using LHTL(Left-Handed Transmission Line) which is a form of a metamaterial and conventional RHTL (Right-Handed Transmission Line), we designed, fabricated and tested a broadband $90^{\circ}$ coupler which is a basic circuit for I-Q vector signal generation. Synthetic LHTL and RHTL were implemented with capacitors and inductors only, that the size is minimized. Also, by implementing a Wilkinson power divider which is required for the suggested circuit using a synthetic RHTL, the size of whole circuit is only $11mm{\times}12mm$. For the frequency range 0.8~1.25 GHz, the phase difference at the outputs maintained $90^{\circ}{\pm}5^{\circ}$ and thus, a broadband $90^{\circ}$ coupler could be made in a compact form. for the same frequency range, the insertion loss is less than 1.6 dB and return loss is more than 10.1 dB. To the best of our knowledge, this is the smallest and broadband $90^{\circ}$ coupler for the frequency range and if the circuit is made with MMIC(Monolithic Microwave Integrated Circuit) technology, the size will be reduced much further.

• Journal of IKEEE
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• v.26 no.1
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• pp.27-35
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• 2022

This paper proposes an ultrasound vessel-pattern imaging algorithm with low computational complexity. The proposed imaging algorithm reconstructs blood-vessel patterns by only detecting blood flow, and can be applied to a real-time signal processing hardware that extracts an ultrasonic finger-vessel pattern. Unlike a blood-flow imaging mode of typical ultrasound medical imaging device, the proposed imaging algorithm only reconstructs a presence of blood flow as an image. That is, since the proposed algorithm does not use an I/Q demodulation and detects a presence of blood flow by accumulating an absolute value of the clutter-filter output, a structure of the algorithm is relatively simple. To verify a complexity of the proposed algorithm, a simulation model for finger vessel was implemented using Field-II program. Through the behavioral simulation, it was confirmed that the processing time of the proposed algorithm is around 54 times less than that of the typical color-flow mode. Considering the required main building blocks and the amount of computation, the proposed algorithm is simple to implement in hardware such as an FPGA and an ASIC.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.225-227
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• 2008

This paper deals with the implementation on a Field Programmable Gate Array (FPGA) of PWM switching patterns for a voltage multilevel inverter. The reference data in main microcontroller is transmitted to the FPGA through 16 general purpose I/O ports. Herein, three-phase reference voltage signals are addressed by the last 2-bit (bit 15-14) and their data are assigned in remaining 14-bit, respectively. The carrier signals are created by 16-bit counter in up-down counting mode inside FPGA according to desirable topology. Each reference signal is compared with all carrier signals to generate corresponding PWM switching patterns for control of the multilevel inverter. Useful advantages of this scheme are easy implementation, simple software control and flexibility in adaptation to produce many PWM signals. Some simulations and experiments are carried out to validate the proposed method.