• Journal of Advanced Marine Engineering and Technology
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• 제35권6호
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• pp.842-848
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• 2011

다중통신을 지원하는 하이브리드 통신 제어보드는 저전력의 8-bit 마이크로콘트롤러인 ATxmega128A1으로 설계하였으며, 마이크로콘트롤러는 다중통신을 위한 모뎀과 GPS 모듈 등을 시리얼 인터페이스 하기 위한 8개의 UART 포트가 갖추어져 있으며, 내부에 2K 바이트의 프로그램 매개변수와 프로그램이 동작하는데 필요한 데이터를 저장할 수 있는 EEPROM과 128K 바이트의 플래시 메모리 및 프로그램이 실행되는 8K 바이트의 SRAM으로 구성되어 있다. 항로표지의 원격 관리를 CDMA, TRS, RF 등 하이브리드 통신을 이용하면 개별 통신 방식별로 음영지역이 존재하는 경우에도, 최적의 통신방식을 선택하여 통신을 수행하게 됨으로써, 통신 음영지역의 해소가 가능하다. 또한 통신장치마다 동일한 데이터 프레임을 사용함으로써 데이터의 호환성을 높였다. 실험은 30일 동안 각 부표에서 매 5분마다 데이터를 취득하였으며, 데이터 수신율은 85 % 이상을 보였다.

• Transactions on Electrical and Electronic Materials
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• 제16권6호
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• pp.293-302
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• 2015

Degraded data stability, weaker write ability, and increased leakage power consumption are the primary concerns in scaled static random-access memory (SRAM) circuits. Two new SRAM cells are proposed in this paper for achieving enhanced read data stability and lower leakage power consumption in memory circuits. The bitline access transistors are asymmetrically gate-underlapped in the proposed SRAM cells. The strengths of the asymmetric bitline access transistors are weakened during read operations and enhanced during write operations, as the direction of current flow is reversed. With the proposed hybrid asymmetric SRAM cells, the read data stability is enhanced by up to 71.6% and leakage power consumption is suppressed up to 15.5%, while displaying similar write voltage margin and maintaining identical silicon area as compared to the conventional memory cells in a 15 nm FinFET technology.

• 한국지진공학회:학술대회논문집
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• 한국지진공학회 2006년도 학술발표회 논문집
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• pp.563-570
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• 2006

Distributed control architecture is based on sharing control and data between multiple nodes on a network Communication and task sharing can be distributed between multiple control computers. Although many communication protocols exist, such as TCP/IP and UDP, they do not have the determinism that realtime control demands. Fiber-optic reflective shared memory creates the opportunity for realtime distributed control. This architecture allows control and computational tasks to be divided between multiple systems and operate in a deterministic realtime environment. One such shared memory architecture is based on Curtiss-Wright ScramNET family of fiber-optic reflective memory. MTS has built seismic and structural control software and hardware capable of utilizing ScramNET shared memory, opening up infinite possibilities in research and new capabilities in Hybrid and Model-In-The-Loop control.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2009년도 정보 및 제어 심포지움 논문집
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• pp.240-242
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• 2009

Flash memories are one of best media to support future computer's storages. However, we need to improve traditional data management scheme due to the relatively slow characteristics of flash operation of SSD. Due to the unique characteristics of flash media and hard disk, the efficiency of I/O processing is severely reduced without special treatment, especially in the presence of heavy workload or bulk data copy. In this respect, we need to design and develop efficient hybrid-RAID storage system.

• Journal of Electrical Engineering and Technology
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• 제11권5호
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• pp.1457-1465
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• 2016

• 한국정보처리학회:학술대회논문집
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• 한국정보처리학회 2013년도 춘계학술발표대회
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• pp.93-96
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• 2013

모바일 환경에서 전력 손실이 중요한 문제 중 하나가 됨에 따라, MRAM과 플래시메모리와 같은 비 휘발성 메모리가 차세대 모바일 컴퓨터에 널리 사용될 것이다. 본 논문에서는 DRAM/MRAM 하이브리드 메인 메모리의 제한적인 쓰기 연산 성능을 고려한 효율적인 버퍼 캐시 기법을 연구했다. 제안한 기법은 MRAM 의 제한적인 쓰기 연산 성능을 고려하고 플래시 메모리 저장 장치의 삭제 연산 횟수를 최소화한다.

• 한국정보과학회논문지:컴퓨팅의 실제 및 레터
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• 제15권1호
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• pp.1-13
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• 2009

플래시 메모리는 크기가 작고, 적은 전력을 사용하며 충격에 강하기 때문에 MP3 플레이어, 핸드폰, 디지털 카메라와 같은 휴대용 기기에서 저장장치로 널리 사용되고 있다. 플래시 메모리의 많은 장점 때문에 개인용 컴퓨터 및 노트북에서 사용되는 저장장치인 하드디스크를 플래시 메모리로 대체하고자 하는 연구도 진행되고 있다. 플래시 메모리는 덮어쓰기가 허용되지 않으며 읽기/쓰기의 기본 단위와 삭제의 기본 단위가 다르기 때문에 FTL(Flash Translation Layer)라는 플래시 변환 계층을 사용한다. 최근에는 기존의 플래시 메모리와 다른 물리구조와 특성을 갖는 대블록 플래시 메모리가 등장하여 기존의 FTL을 그대로 사용하게 되면 플래시 메모리를 효율적으로 사용할 수 없다. 본 논문에서는 기존의 FTL 중 가장 좋은 성능을 내는 FAST(Fully Associative Sector Translation)을 기반으로 데이타블록 내에서 페이지단위 사상을 적용하여 대블록 플래시 메모리의 특성에 맞는 FTL 기법을 제안한다.

• JSTS:Journal of Semiconductor Technology and Science
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• 제2권2호
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• pp.111-124
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• 2002

The ferroelectric RAM (FeRAM) has a great advantage for a system on a chip (SOC) and mobile product memory, since FeRAM not only supports non-volatility but also delivers a fast memory access similar to that of DRAM and SRAM. This work develops at three levels: 1) low voltage operation with boost voltage control of bitline and plateline, 2) reducing bitline capacitance with multiple divided sub cell array, and 3) increasing chip performance with write operation sharing both active and precharge time period. The key techniques are implemented on the proposed hierarchy bitline scheme with proposed hybrid-bitline and high voltage boost control. The test chip and simulation results show the performance of sub-1.5 voltage operation with single step pumping voltage and self-boost control in a cell array block of 1024 ($64{\;}{\times}{\;}16$) rows and 64 columns.

• Journal of information and communication convergence engineering
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• 제21권2호
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• pp.159-166
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• 2023

The COI gene is a sequence of approximately 650 bp at the 5' terminal of the mitochondrial Cytochrome c Oxidase subunit I (COI) gene. As an effective DeoxyriboNucleic Acid (DNA) barcode, it is widely used for the taxonomic identification and evolutionary analysis of species. We created a CNN-LSTM hybrid model by combining the gene features partially extracted by the Long Short-Term Memory ( LSTM ) network with the feature maps obtained by the CNN. Compared to K-Means Clustering, Support Vector Machines (SVM), and a single CNN classification model, after training 278 samples in a training set that included 15 genera from two orders, the CNN-LSTM hybrid model achieved 94% accuracy in the test set, which contained 118 samples. We augmented the training set samples and four genera into four orders, and the classification accuracy of the test set reached 100%. This study also proposes calculating the cosine similarity between the training and test sets to initially assess the reliability of the predicted results and discover new species.

• 반도체디스플레이기술학회지
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• 제22권4호
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• pp.38-47
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• 2023

Three dimensional (3D) packaging is a next-generation packaging technology that vertically stacks chips such as memory devices. The necessity of 3D packaging is driven by the increasing demand for smaller, high-performance electronic devices (HPC, AI, HBM). Also, it facilitates innovative applications across another fields. With growing demand for high-performance devices, companies of semiconductor fields are trying advanced packaging techniques, including 2.5D and 3D packaging, MR-MUF, and hybrid bonding. These techniques are essential for achieving higher chip integration, but challenges in mass production and fine-pitch bump connectivity persist. Advanced bonding technologies are important for advancing the semiconductor industry. In this review, it was described 3D packaging technologies for chip integration including mass reflow, thermal compression bonding, laser assisted bonding, hybrid bonding.