• Journal of the Korea Society of Computer and Information
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• v.24 no.7
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• pp.1-8
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• 2019

Recently, an SSD with hybrid buffer memories is actively researching to reduce the overall latency in server computing systems. However, existing hybrid buffer policies caused many swapping operations in pages because it did not consider the overall latency such as read/write operations of flash chips in the SSD. This paper proposes the clock with hybrid buffer memories (CLOCK-HBM) for a new hybrid buffer policy in the SSD with server computing systems. The CLOCK-HBM constructs new policies based on unique characteristics in both DRAM buffer and NVMs buffer for reducing the number of swapping operations in the SSD. In experimental results, the CLOCK-HBM reduced the number of swapping operations in the SSD by 43.5% on average, compared with LRU, CLOCK, and CLOCK-DNV.

• Journal of the Semiconductor & Display Technology
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• v.20 no.4
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• pp.10-15
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• 2021

Cache bypassing schemes have been studied to remove unnecessary updating the data in cache blocks. Among them, a statistics-based cache bypassing method for asymmetric-access caches is one of the most efficient approach for non-voliatile memories and shows the lowest cache access latency. However, it is proposed under the condition of the normal cache system, so further study is required for the hybrid cache architecture. This paper proposes a novel cache bypassing scheme, called hybrid bypassing block selector. In the proposal, the new model is established considering the SRAM region and the non-volatile memory region separately. Based on the model, hybrid bypassing decision block is implemented. Experiments show that the hybrid bypassing decision block saves overall energy consumption by 21.5%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.31-37
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• 2006

Low-density parity-check (LDPC) codes are recently emerged due to its excellent performance. The standard for European high definition satellite digital video broadcast, DVB-S2 has adopted LDPC codes as a channel coding scheme. This paper proposes a DVB-S2 LDPC decoder architecture using a hybrid parity check matrix which is efficient in hardware implementation for both decoders and encoders. The hybrid H-matrices are constructed so that both the semi-random technique and the partly parallel structure can be applied to design encoders and decoders. Using the hybrid H-matrix scheme, the architecture of LDPC decoder for DVB-S2 can be very practical and efficient. In addition, we show a new Variable Node processor Unit (VNU) architecture to reuse the VNU for various code rates and optimized block memory placement to reuse. We design a DVB-S2 LDPC decoder of code rate 1/2 usng the proposed architecture. We estimate the performance of the DVB-S2 LDPC decoder and compare it with other decoders.

• Journal of the Korea Society of Computer and Information
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• v.22 no.3
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• pp.1-8
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• 2017

In this paper, we propose a new hybrid wear leveling technique for NAND Flash memory, called Time-Aware Wear Leveling (TAWL). Our proposal prolongs the lifetime of NAND Flash memory by using dynamic wear leveling technique which considers the wear level of hot blocks as well as static wear leveling technique which considers the wear level of the whole blocks. TAWL also reduces the overhead of garbage collection by separating hot data and cold data using update frequency rate. We showed that TAWL enhanced the lifetime of NAND flash memory up to 220% compared with previous wear leveling techniques and our technique also reduced the number of copy operations of garbage collections by separating hot and cold data up to 45%.

• Journal of KIISE
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• v.43 no.2
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• pp.177-185
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• 2016

In this paper, we propose a hybrid write buffer architecture comprised of DRAM and NVRAM on SSD and a write buffer algorithm for the hybrid write buffer architecture. Unlike other write buffer algorithms, the proposed algorithm considers read pages as well as write pages to improve the performance of storage devices because most actual workloads are read-write mixed workloads. Through effectively managing NVRAM pages, the proposed algorithm extends the endurance of SSD by reducing the number of erase operations on NAND flash memory. Our experimental results show that our algorithm improved the buffer hit ratio by up to 116.51% and reduced the number of erase operations of NAND flash memory by up to 56.66%.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.23 no.4
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• pp.53-58
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• 2023

As smartphones increasingly support the execution of various applications, the function of virtual memory swapping is becoming important. However, unlike traditional computer systems, mobile platforms do not basically support swapping. This is because swapping results in frequent writes to flash memory, which may degrade the performance of smartphone's storage significantly. To cope with this situation, this paper suggests two multi-swap architectures, hierarchical swapping and hybrid swapping, and compares their performance quantitatively. Specifically, this paper shows that hybrid swapping with the consideration of single-access data can reduce swapping traffic to flash memory, and improve the performance compared to traditional swapping.

• International Journal of Aeronautical and Space Sciences
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• v.8 no.2
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• pp.76-81
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• 2007

The fiber reinforced laminated composite structures are very susceptible to be damaged when they are impacted by foreign objects. To increase the impact resistance of the laminated composite structures, shape memory alloy(SMA) thin film is embedded in the structure. For the numerical impact analysis of SMA hybrid composite structures, SMA modeling tool is developed to consider pseudoelastic effect of SMAs. Moreover, the damage analysis is considered using failure criteria and a simple damage model for reasonable impact analysis. The numerical results are verified with the experimental ones. Impact analyses for composite plate with pre-strained SMAs are numerically performed and the damage areas are investigated.

• IEMEK Journal of Embedded Systems and Applications
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• v.9 no.2
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• pp.101-107
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• 2014

Mobile robots use an environment map of its workspace to complete the surveillance task. However grid-based maps that are commonly used map format for mobile robot navigation use a large size of memory for accurate representation of environment. In this reason, grid-based maps are not suitable for path planning of mobile robots using embedded board. In this paper, we present the path planning algorithm that produce a secure path rapidly. The proposed approach utilizes a hybrid map that uses less memory than grid map and has same efficiency of a topological map. Experimental results show that the fast path planning uses only 1.5% of the time that a grid map based path planning requires. And the results show a secure path for mobile robot.

• Earthquakes and Structures
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• v.25 no.1
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• pp.15-26
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• 2023

It is of great importance to assess the residual displacement demand in the performance-based seismic design. In this paper, a hybrid deep learning model for predicting the residual displacement spectra under near-fault (NF) ground motions is proposed by combining the long short-term memory network (LSTM) and back-propagation (BP) network. The model is featured by its capacity of predicting the residual displacement spectrum under a given NF ground motion while considering the effects of structural parameters. To construct this model, 315 natural and artificial NF ground motions were employed to compute the residual displacement spectra through elastoplastic time history analysis considering different structural parameters. Based on the resulted dataset with a total of 9,450 samples, the proposed model was finally trained and tested. The results show that the proposed model has a satisfactory accuracy as well as a high efficiency in predicting residual displacement spectra under given NF ground motions while considering the impacts of structural parameters.

• Proceedings of the Korean Vacuum Society Conference
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• 2013.02a
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• pp.311-311
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• 2013

The resistance switching memory devices have several advantages to take breakthrough for the limitation of operation speed, retention, and device scale. Especially, the metal-oxide materials such as ZnO are able to fabricate on the flexible and visible transparent plastic substrate. Also, the quantum dots (QDs) embedded in dielectric layer could be improve the ratio between the low and the high resistance becauseof their Coulomb blockade, carrier trap and induced filament path formation. In this study, we irradiated 0.2-MeV-electron beam on the ZnO/QDs/ZnO structure to control the defect and oxygen vacancy of ZnO layer. The metal-oxide QDs embedded in ZnO layer on Pt/glass substrate were fabricated for a memory device and evaluated electrical properties after 0.2-MeV-electron beam irradiations. To formation bottom electrode, the Pt layer (200 nm) was deposited on the glass substrate by direct current sputter. The ZnO layer (100 nm) was deposited by ultra-high vacuum radio frequency sputter at base pressure $1{\times}10^{-10}$ Torr. And then, the metal-oxide QDs on the ZnO layer were created by thermal annealing. Finally, the ZnO layer (100 nm) also was deposited by ultra-high vacuum sputter. Before the formation top electrode, 0.2 MeV liner accelerated electron beams with flux of $1{\times}10^{13}$ and $10^{14}$ electrons/$cm^2$ were irradiated. We will discuss the electrical properties and the physical relationships among the irradiation condition, the dislocation density and mechanism of resistive switching in the hybrid memory device.