• 대한전자공학회논문지SD
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• 제40권9호
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• pp.638-643
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• 2003

Channel width dependence of hot-carrier effect in nMOSFET with shallow trench isolation is analyzed. $I_{sub}$- $V_{G}$ and $\Delta$ $I_{ㅇ}$ measurement data show that MOSFETs with narrow channel-width are more susceptible to the hot-carrier degradation than MOSFETs with wide channel-width. By analysing $I_{sub}$/ $I_{D}$, linear $I_{D}$- $V_{G}$ characteristics, thicker oxide-thickness at the STI edge is identified as the reason for the channel-width dependent hot-carrier degradation. Using the charge-pumping method, $N_{it}$ generation due to the drain avalanche hot-carrier (DAHC) and channel hot-electron (CHE) stress are compared. are compared.

• 한국정밀공학회지
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• 제28권1호
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• pp.63-72
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• 2011

In recent years, hot-stamped components are more increasingly used in the automotive industry in order to reduce weight and to improve the strength of vehicles. In hot stamping process, blank is hot formed and press hardened in a tool. However, in hot stamping without cooling channel, temperature of the tool increases gradually in mass production thus cannot meet the critical cooling rate to obtain high strength over 1500MPa. Warpage occurs in the hot stamped component due to non-uniform stress state caused by unbalanced cooling. Therefore, tools should be uniformly as well as rapidly cooled down by the coolant which flows through cooling channel. In this paper, optimal design method of cooling channel to obtain uniform and high strength of the component is proposed. Optimized cooling channel is applied to the hot press V-bending process. As a result of measuring strength, hardness and microstructure of the hot formed parts, it is known that the design methodology of cooling channel is effective to the hot stamping process.

• Nuclear Engineering and Technology
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• 제20권2호
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• pp.80-87
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• 1988

소형냉각재상실사고(SBLOCA)와 대형냉각재상실사고(LBLOCA)중에 노심의 Average Channel과 Hot Channel에서의 유량분포를 예측하였다. 아울러 REALP5/MOD2 코드를 사용하여 두 채널사이의 교차류고려여부가 실제사고 분석결과에 미치는 영향을 평가하였다. 현재까지 SBLOCA계산에서는 노심을 한개의 채널로 모델하는 것이 충분하다고 판단되어 왔으나 본 계산결과에 의하면 보수적인 계산을 위해서는 Hot Channel 모델링이 필요한 것으로 밝혀졌다. 그러나 LBLOCA Blowdown Phase존에서는 교차류의 고려 여부에 상관없이 Hot Channel 이 Average Channel보다 보수적 인 결과를 가져오며, 교차류의 영향도 미세한 것으로 판명되었다.

• 대한기계학회논문집A
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• 제33권11호
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• pp.1267-1273
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• 2009

Hot press forming can produce high-strength components by rapidly cooling between closed punch and die after hot forming using quenchable boron steel austenized in a furnace. In the hot press forming process, the cooling rate is influenced by the size, position and arrangement of the cooling channel and the file condition of cooling water in the die. Also, mechanical properties of the final components and operation time are related to cooling rate. Therefore, the design of optimized cooling channel is one of the most important works. In this paper, the effect of position and size of the cooling channel on the cooling rate was investigated by using design of experiment and FE analysis in hot press bending process. Therefore the optimum cooling channel ratio was presented in the HPB.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2015년도 추계학술대회
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• pp.889-893
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• 2015

본 연구에서는 채널 폭 변화에 따른 나노와이어 GAA 소자의 GIDL 전류 (Gate Induced Drain Leakage Current)를 측정하고, hot carrier 스트레스를 인가하였을 때 소자의 GIDL전류특성 변화를 분석하였다. 소자의 길이는 250nm로 고정시키고 채널 폭이 10nm, 50nm, 80nm, 130nm인 소자들을 사용하여 측정하였다. 스트레스 전의 소자를 측정한 결과 채널 폭이 감소할수록 GIDL전류가 증가하였고, 채널 폭이 증가할수록 구동전류는 증가함을 확인하였다. Hot carrier 스트레스에 따른 GIDL 전류 측정값의 변화율은 채널 폭이 감소할수록 큰 변화율을 보였다. 또한, 채널 폭이 감소할수록 또 hot carrier 스트레스 후 GIDL 전류가 증가하는 이유를 소자 시뮬레이션을 통하여 확인하였다.

• 한국정보통신학회논문지
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• 제9권8호
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• pp.1649-1655
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• 2005

동위상(I) 파일럿 채널에 할당된 셀룰러 셀 CCSSC와 직교위상(Q) 파일럿 채널에 할당된 핫 스팟 셀 HSCSSC가 공존하는 광대역 OFCDM 시스템에 환경하에서 분리된 I/Q채널 CCSC를 이용한 탐색 알고리즘을 제안하였다. 제안된 알고리즘은 이동 기지국에서 무선 인터넷을 사용하고자 할 때 셀룰러 셀 CCSSC의 영향으로 감소하는 최상의 핫 스팟 셀 HSCSSC을 빠르게 추적하는데 적합하다. 시뮬레이션 결과 제안된 셀 추적 알고리즘이 기존의 셀 추적 알고리즘과 비교하여 훨씬 빠른 결과를 수행할 수 있음을 보였다.

• 소성∙가공
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• 제25권4호
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• pp.242-247
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• 2016

CFD simulation with FlowVision^® is used to evaluate the capability of cooling channel in hot press forming dies. Two different types of cooling channels, dry drilled and pocket types are considered for comparison. Two different approaches for simulating cooling channel are considered. One is single-phase velocity calculation for coolant only and the other is multiphase thermal and velocity calculation for die, blank and coolant all together. Both approaches show better cooling performance in pocket type cooling channel. Also both approaches show their own effectiveness in designing cooling channel of hot press forming dies.

• 전자공학회논문지A
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• 제33A권10호
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• pp.130-138
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• 1996

The size of a device needs to scale down to increase its integrity and speed. As the size of the device is reduced, the hot-carrier degradation that severely effects on device reliabilty is concerned. In this paper, sub-micron buried-channel P-MOSFETs were fabircated, and the hot-carrier effects were invetigated. Also the hot-carrier effect in the buired-channel P-MOSFETs and the surface-channel P-MOSFETs were compared with simulation programs using SUPREM-4 and MINIMOS-4. This paper showed that the electric characteristics of sub-micron P-MOSFET are different from those of N-MOSFET. Also it showed that the punchthrough voltage ( $V_{pt}$ ) was abruptly drop after applying the stress and became almost 0V when the channel lengths were shorter than 0.6.mu.m. The lower punchthrough voltage causes the device to operte poorly by the deterioration of cut-off characteries in the switching mode. We can conclude that the buried channel P-MOSFET for CMOS circuits has a limit of the channel length to be around 0.6.mu.m.

• 대한전기학회:학술대회논문집
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• 대한전기학회 1998년도 하계학술대회 논문집 D
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• pp.1367-1369
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• 1998

To achieve the ULSI goals of higher density, greater performance and operation speed have been scaled down. However, the reduction of channel length cause undesirable problems such as drop of punchthrough voltage, hot-carrier degradation and high leakage current, etc.. It is shown that the device characteristics depend on process parameters. In this Paper, we catched hold of trends of hot-carrier effects and punchthrough voltages due to variation of some process parameters such as LDD doses(P), spacer lengths, channel doses($BF_2$) and $V_T$ adjusting channel implantation energies using design trend curve (DTC). As the LDD and channel doses increased, hot-carrier phenomena became more severe, and punchthrough voltage was decreased. It were represented that punchthrough and hot carrier effects were critically depend on LDD and channel doses.

• 전자공학회논문지A
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• 제28A권12호
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• pp.53-58
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• 1991

Hot-carrier induced degradation has been studied for the BF$_2$ ion-implanted surface-channel LDD(P$^{+}$ polysilicon gate) PMOSFET in comparison to the buried-channel structure(N$^{+}$ polysilicon gate) PMOSFET. The conditions for maximum degradation better correlated to I$_{g}$ than I$_{sub}$ for both PMOSFET's. Due to the use of LDD structure on SC-PMOSFET, the substrate current for SC-PMOSFET was shown to be smaller than that of BC-PMOSFET. The gate current was smaller as well, due to the gate material work-function difference between p$^{+}$ and n$^{+}$ polysilicon gates. From the results, it was shown that the surface-channel LDD PMOSFET is more resistant to short channel effect than the buried-channel PMOSFET.