• Proceedings of the KIEE Conference
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• 2006.07d
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• pp.2061-2062
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• 2006

a-Si(amorphous silicon) TFT(thin film transistor)는 TFT-LCD(liquid crystal display)의 화소 스위칭(switching) 소자로 폭넓게 이용되고 있다. 현재는 a-Si을 이용하여 gate drive IC를 기판에 집적하는 ASG(amorphous silicon gate) 기술이 연구, 적용되고 있는데 이때 가장 큰 제약은 문턱 전압(Vth)의 이동이다. 특히 고온에서는 문턱 전압의(Vth) 이동이 가속화 되고, Ioff current가 증가 하게 되고, 저온($0^{\circ}C$)에서는 전류 구동능력이 상온($25^{\circ}C$) 상태에서 같은 게이트 전압(Vg)에 대해서 50% 수준으로 감소하게 된다. 특히 ASG 회로는 여러 개의 TFT로 구성되는데, 각각의 TFT가 고온에서 Vth shift 값이 다르게 되어 설계시 예상하지 못 한 고온에서의 화면 무너짐 현상 즉 고온 노이즈 불량이 발생 할 수 있다. 고온 노이즈 불량은 고온에서의 각 TFT의 문턱전압 및 $I_D-V_G$ 특성을 측정한 결과 고온 노이즈 불량에 영향을 주는 인자가 TFT의 width와 기생 capacitor비 hold TFT width가 영향을 주는 것으로 실험 및 시뮬레이션 결과 확인이 되었다. 발생 mechanism은 ASG 회로는 AC 구동을 하기 때문에 Voff 전위에 ripple이 발생 되는데 특히 고온에서 ripple이 크게 증가 하여 출력 signal에 영향을 주어 불량이 발생하는 것을 규명하였다.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.4
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• pp.524-533
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• 2017

This paper presents a novel reset scheme for mm-scale sensing systems with stringent volume and area constraints. In such systems, multi-layer structure is required to maximize the silicon area per volume and minimize the system size. The multi-layer structure requires wirebonding connections for power delivery and communication among layers, but the area overhead for wirebonding pads can be significant. The proposed reset scheme exploits already existing power wires and thus does not require additional wires for system-wide reset operation. To implement the proposed reset scheme, a power management unit is designed to impose reset condition, and a reset detector is designed to interpret the reset condition indicated by the power wires. The reset detector uses a coupling capacitor for the initial power-up and a feedback path to hold the developed supply voltage. The prototype reset detector is fabricated in a $180-{\mu}m$ CMOS process, and the measurement results with the prototype mm-scale system confirmed robust reset operation over a wide range of temperatures and voltages.

• Journal of the Korean Chemical Society
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• v.36 no.5
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• pp.674-678
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• 1992

An instrument is described that can obtain directly the whole capacitance vs. potential curve and accurately even in dilute solutions using positive feedback for IR correction. Applying a small (7∼10 mV) triangular signal, controlled rectification of the resulting square wave using sample-and-hold circuit allows one to plot the corrected double layer capacitance over a wide potential range. Several illustrations involving the improved performance characteristics of its applicability are given and its limitations discussed.

• Smart Structures and Systems
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• v.1 no.4
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• pp.325-338
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• 2005

Utilizing robotic based reconfigurable nodal structural health monitoring systems has many advantages over static or human positioned sensor systems. However, creating a robot capable of traversing a variety of civil infrastructures is a difficult task, as these structures each have unique features and characteristics posing a variety of challenges to the robot design. This paper outlines the design and implementation of a novel robotic platform for deployment on ferromagnetic structures as an enabling structural health monitoring technology. The key feature of this design is the utilization of an attachment device which is an advancement of the common magnetic base found in the machine tool industry. By mechanizing this switchable magnetic circuit and redesigning it for light weight and compactness, it becomes an extremely efficient and robust means of attachment for use in various robotic and structural health monitoring applications. The ability to engage and disengage the magnet as needed, the very low power required to do so, the variety of applicable geometric configurations, and the ability to hold indefinitely once engaged make this device ideally suited for numerous robotic and distributed sensor network applications. Presented here are examples of the mechanized variable force magnets, as well as a prototype robot which has been successfully deployed on a large construction site. Also presented are other applications and future directions of this technology.

• Transactions of the Korean Society of Mechanical Engineers
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• v.12 no.5
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• pp.968-975
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• 1988

The maximum feedrate generated from the hardware DDA is closely related to its calculation efficiency. The smaller interpolation span results in the lower calculation efficiency. This paper presents the method to improve the calculation efficiency for the smaller interpolation span. For the linear interpolation the higher calculation efficiency can be achieved by putting biggest value that the interpolation DDA can hold. for the circular interpolation, however, the scheme used for linear interpolation does not work since arbitrary change of value in the interpolation DDA changes the radius of the circle. The bit length of the hardware DDA is adjusted instead of adjusting the value in DDA, which results in the every same effect on calculation efficiency for the circular interpolation. The hardware circuit and supporting software are designed, and tested by two axis step motor driven milling machine. The experimental results show that the proposed method drastically increases the maximum feedrate even for the smaller interpolation span.

• Journal of Ceramic Processing Research
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• v.13 no.spc2
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• pp.308-311
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• 2012

A wide range of possible hazards existing in thermal batteries are mainly caused by thermal runaway, which results in overheating or explosion in extreme case. Battery separators ensure the separation between two electrodes and the retention of ion-conductive electrolytes. Thermal runaways in thermal batteries can be significantly reduced by the adoption of these separators. The high operating temperature and the violent reactivity in thermal batteries, however, have limited the introduction of conventional separators. As a substitute for separators, MgO powders have been mostly used as a binder to hold molten salt electrolyte. During recent decades the fabrication technology of ceramic fiber, which has excellent mechanical strength and chemical stability, has undergone significant improvement. In this study we adopted wet-laid nonwoven paper making method instead of the electrospinning method which is costly and troublesome to produce in volume. Polymeric precursor can readily be coated on the surface of wet-laid ceramic paper, and be formed into ceramic film after heat treatment. The mechanical strength and the thermo-chemical stability as well as the wetting behaviors of ceramic separators with various molten salts were investigated to be applicable to thermal batteries. Due to their excellent chemical, mechanical, and electrical properties, wet-laid nonwoven separators made from ceramic fibers have revealed positive possibility as new separators for thermal batteries which operate at high temperature with no conspicuous sign of a short circuit and corrosion.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.6 s.336
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• pp.1-8
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• 2005

In this paper, CMOS A/D converter with 6bit 2GSPS Nyquist input at 1.8V is designed. In order to obtain the resolution of 6bit and the character of high-speed operation, we present an Interpolation type architecture. In order to overcome the problems of high speed operation, a novel One-zero Detecting Encoder, a circuit to reduce the Reference Fluctuation, an Averaging Resistor and a Track & Hold, a novel Buffered Reference for the improved SNR are proposed. The proposed ADC is based on 0.18um 1-poly 3-metal N-well CMOS technology, and it consumes 145mW at 1.8V power supply and occupies chip area of 977um $\times$ 1040um. Experimental result show that SNDR is 36.25 dB when sampling frequency is 2GHz and INL/DNL is $\pm$0.5LSB at static performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.5
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• pp.658-665
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• 2014

The neural stimulators have been employed to the visual prostheses system based on the functional electrical stimulation (FES). Due to the size limitation of the implantable device, the smaller area of the unit current driver pixel is highly desired for higher resolution current stimulation system. This paper presents a 16-channel compact current-mode neural stimulator IC with digital to analog converter (DAC) sharing scheme for artificial retinal prostheses. The individual pixel circuits in the stimulator IC share a single 6 bit DAC using the sample-and-hold scheme. The DAC sharing scheme enables the simultaneous stimulation on multiple active pixels with a single DAC while maintaining small size and low power. The layout size of the stimulator circuit with the DAC sharing scheme is reduced to be 51.98 %, compared to the conventional scheme. The stimulator IC is designed using standard $0.18{\mu}m$ 1P6M process. The chip size except the I/O cells is $437{\mu}m{\times}501{\mu}m$.

• Journal of information and communication convergence engineering
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• v.10 no.1
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• pp.85-90
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• 2012

A 40-MS/sec 10-bit pipelined analog to digital converter (ADC) with a 1.2 Vpp differential input signal is proposed. The implemented pipelined ADC consists of eight stages of 1.5 bit/stage, one stage of 2 bit/stage, a digital error correction block, band-gap reference circuit & reference driver, and clock generator. The 1.5 bit/stage consists of a sub-ADC, digital to analog (DAC), and gain stage, and the 2.0 bit/stage consists of only a 2-bit sub-ADC. A bootstrapped switch with a constant resistance is proposed to improve the linearity of the input switch. It reduces the maximum VGS variation of the conventional bootstrapped switch by 67%. The proposed bootstrapped switch is used in the first 1.5 bit/stage instead of a sample-hold amplifier (SHA). This results in the reduction of the hardware and power consumption. It also increases the input bandwidth and dynamic performance. A reference voltage for the ADC is driven by using an on-chip reference driver without an external reference. A digital error correction with a redundancy is also used to compensate for analog noise such as an input offset voltage of a comparator and a gain error of a gain stage. The proposed pipelined ADC is implemented by using a 0.18-${\mu}m$ 1- poly 5-metal CMOS process with a 1.8 V supply. The total area including a power decoupling capacitor and the power consumption are 0.95 $mm^2$ and 51.5 mW, respectively. The signal-to-noise and distortion ratio (SNDR) is 56.15 dB at the Nyquist frequency, resulting in an effective number of bits (ENOB) of 9.03 bits.

• Journal of the Korean Society for Railway
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• v.10 no.6
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• pp.645-649
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• 2007

Ground systems flow fault currents into the ground, and suppress Ground Potential Rise (GPR) by the current. In this paper, we designed and fabricated a surge impedance meter to analyze the ground impedance in wide frequency ranges. The meter consists of a surge generator, a high speed sample/hold (S/H) circuit and an associated electronics. The surge generator produces surge voltage up to 5kV in ranges of $50\sim500ns$. Field tests were carried out to evaluate the surge impedance meter at a driven-rod ground system. The results showed that surge impedance of ground systems should be measured by various fast surge waveforms, since the impedance increases as the rise time of applied voltage increases.